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W49V002AQ PDF даташит

Спецификация W49V002AQ изготовлена ​​​​«Winbond» и имеет функцию, называемую «256K x 8 CMOS FLASH MEMORY WITH LPC INTERFACE».

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Номер произв W49V002AQ
Описание 256K x 8 CMOS FLASH MEMORY WITH LPC INTERFACE
Производители Winbond
логотип Winbond логотип 

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W49V002AQ Даташит, Описание, Даташиты
Preliminary W49V002A
256K x 8 CMOS FLASH MEMORY
WITH LPC INTERFACE
GENERAL DESCRIPTION
The W49V002A is a 2-megabit, 3.3-volt only CMOS flash memory organized as 256K × 8 bits. The
device can be programmed and erased in-system with a standard 3.3V power supply. A 12-volt VPP is
not required. The unique cell architecture of the W49V002A results in fast program/erase operations with
extremely low current consumption. This device can operate at two modes, Programmer bus interface
mode and LPC bus interface mode. As in the Programmer interface mode, it acts like the traditional
flash but with a multiplexed address inputs. But in the LPC interface mode, this device complies with the
Intel LPC specification 1.0. The device can also be programmed and erased using standard EPROM
programmers.
FEATURES
Single 3.3-volt operations:
3.3-volt Read
3.3-volt Erase
3.3-volt Program
Fast Program operation:
Byte-by-Byte programming: 50 µS (typ.)
Fast Erase operation: 150 mS (typ.)
Endurance: 10K cycles (typ.)
Twenty-year data retention
Hardware data protection
#TBL & #WP serve as hardware protection
One 16K bytes Boot Block with lockout
protection
Two 8K bytes Parameter Blocks
Four Main Memory Blocks (with 32K bytes, 64K
bytes, 64K bytes, 64K bytes each)
Low power consumption
Active current: 25 mA (typ.)
Standby current: 20 µA (typ.)
Automatic program and erase timing with
internal VPP generation
End of program or erase detection
Toggle bit
Data polling
Latched address and data
TTL compatible I/O
Available packages: 32L PLCC and 32L
STSOP
Publication Release Date: April 2001
- 1 - Revision A1









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W49V002AQ Даташит, Описание, Даташиты
Preliminary W49V002A
PIN CONFIGURATIONS
NC
NC
NC
GND
MODE
A10(GPI4)
R/#C(CLK)
VDD
NC
#RESET
A9(GPI3)
A8(GPI2)
A7(GPI1)
A6(GPI0)
A5(#WP)
A4(#TBL)
A
8
^
G
P
I
2
v
A
9
^#
GR
PE
IS
V
3 END
v T CD
R
#
C
^
C
L
K
v
A
1
0
^
G
P
I
4
v
4 3 2 1 32 31 30
A7(GPI1)
A6(GPI0)
A5(#WP)
A4(#TBL)
A3(RSV)
A2(RSV)
A1(RSV)
A0(RSV)
DQ0(LAD0)
5 29
6 28
7 27
8
32-pin
26
9
PLCC
25
10 24
11 23
12 22
13 21
14 15 16 17 18 19 20
MODE
GND
NC
NC
VDD
#OE(#INIT)
#WE(#LFRAM)
NC
DQ7(RSV)
DD G D DD D
QQ N QQ Q Q
12D3 4 5 6
^^
^^ ^ ^
LL
L RR R
AA
A S SS
DD
D V VV
12
3vvv
vv
v
1
2
3
4
5
6
7
8 32-pin
9 TSOP
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
#OE(#INIT)
#WE(#LFRAM)
NC
DQ7(RSV)
DQ6(RSV)
DQ5(RSV)
DQ4(RSV)
DQ3(LAD3)
GND
DQ2(LAD2)
DQ1(LAD1)
DQ0(LAD0)
A0(RSV)
A1(RSV)
A2(RSV)
A3(RSV)
BLOCK DIAGRAM
#WP
#TBL
CLK
LAD[3:0]
#LFRAM
MODE
#INIT
#RESET
LPC
Interface
R/#C
A[10:0]
DQ[7:0]
#OE
#WE
Program-
mer
Interface
BOOT BLOCK
16K BYTES
PARAMETER
BLOCK1
8K BYTES
PARAMETER
BLOCK2
8K BYTES
MAIN MEMORY
BLOCK1
32K BYTES
MAIN MEMORY
BLOCK2
64K BYTES
MAIN MEMORY
BLOCK3
64K BYTES
MAIN MEMORY
BLOCK4
64K BYTES
3FFFF
3C000
3BFFF
3A000
39FFF
38000
37FFF
30000
2FFFF
20000
1FFFF
10000
0FFFF
00000
PIN DESCRIPTION
SYMB INTERFACE
PIN NAME
PGM LPC
MODE
*
* Interface Mode Selection
#RESET *
* Reset
#INIT
* Initialize
#TBL
* Top Boot Block Lock
#WP
* Write Protect
CLK * CLK Input
GPI[4:0]
* General Purpose
Inputs
LAD[3:0]
* Address/Data Inputs
#LFRAM
* LPC Cycle Initial
R/#C
*
Row/Column Select
A[10:0]
*
Address Inputs
DQ[7:0] *
Data Inputs/Outputs
#OE
*
Output Enable
#WE
*
Write Enable
VDD * * Power Supply
GND
*
* Ground
RSV * * Reserve Pins
NC * * No Connection
-2-









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W49V002AQ Даташит, Описание, Даташиты
Preliminary W49V002A
FUNCTIONAL DESCRIPTION
Interface Mode Selection And Description
This device can be operated in two interface modes, one is Programmer interface mode, the other is LPC
interface mode. The MODE pin of the device provides the control between these two interface modes.
These interface modes need to be configured before power up or return from #RESET. When MODE pin
is set to high state, the device is in the Programmer mode; while the MODE pin is set to low state(or
leaved no connection), it is in the LPC mode. In Programmer mode, this device just behaves like
traditional flash parts with 8 data lines. But the row and column address inputs are multiplexed, which go
through the address inputs A[10:0]. For LPC mode, It complies with the LPC Interface Specification
Revision 1.0. Through LAD[3:0] to communicate with the system chipset .
Read(Write) Mode
In Programmer interface mode, the read(write) operation of the W49V002A is controlled by #OE (#WE).
The #OE (#WE) is held low for the host to obtain(write) data from(to) the outputs(inputs). #OE is the
output control and is used to gate data from the output pins. The data bus is in high impedance state
when #OE is high. As in the LPC interface mode, the read or write is determined by the "bit 1 of CYCLE
TYPER+DIR".
Reset Operation
The #RESET input pin can be used in some application. When #RESET pin is at high state, the device
is in normal operation mode. When #RESET pin is at low state, it will halt the device and all outputs will
be at high impedance state. As the high state re-asserted to the #RESET pin, the device will return to
read or standby mode, it depends on the control signals.
Chip Erase Operation
The chip-erase mode can be initiated by a six-byte command sequence. After the command loading
cycle, the device enters the internal chip erase mode, which is automatically timed and will be
completed within fast 100 mS (typical). The host system is not required to provide any control or timing
during this operation. If the boot block programming lockout is activated, only the data in the other
memory blocks will be erased to FF(hex) while the data in the boot block will not be erased (remains as
the same state before the chip erase operation). The entire memory array will be erased to FF(hex) by
the chip erase operation if the boot block programming lockout feature is not activated. The device will
automatically return to normal read mode after the erase operation completed. Data polling and/or Toggle
Bits can be used to detect end of erase cycle.
Sector Erase Operation
The seven sectors, one boot block and two parameter blocks and four main blocks, can be erased
individually by initiating a six-byte command sequence. Sector address is latched on the falling #WE
edge of the sixth cycle, while the 30(hex) data input command is latched at the rising edge of #WE.
After the command loading cycle, the device enters the internal sector erase mode, which is
automatically timed and will be completed within fast 150 mS (typical). The host system is not required
to provide any control or timing during this operation. The device will automatically return to normal read
mode after the erase operation completed. Data polling and/or Toggle Bits can be used to detect end of
erase cycle.
Program Operation
The W49V002A is programmed on a byte-by-byte basis. Program operation can only change logical data
Publication Release Date: April 2001
- 3 - Revision A1










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Номер в каталогеОписаниеПроизводители
W49V002A256K x 8 CMOS FLASH MEMORY WITH LPC INTERFACEWinbond
Winbond
W49V002AP256K x 8 CMOS FLASH MEMORY WITH LPC INTERFACEWinbond
Winbond
W49V002AQ256K x 8 CMOS FLASH MEMORY WITH LPC INTERFACEWinbond
Winbond

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