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W6662CF PDF даташит

Спецификация W6662CF изготовлена ​​​​«Winbond» и имеет функцию, называемую «SCANNER ANALOG FRONT END».

Детали детали

Номер произв W6662CF
Описание SCANNER ANALOG FRONT END
Производители Winbond
логотип Winbond логотип 

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W6662CF Даташит, Описание, Даташиты
Preliminary W6662CF
SCANNER ANALOG FRONT END
1. GENERAL DESCRIPTION
The W6662 is a highly integrated CCD/CIS analog front end signal processor. It provides the
components required for all necessary front-end signal process of a CCD/CIS scanner, including a 3-
channel input clamp circuit for correlated double sampling (short as CDS) mode, a multiplexer to mux
3-channel inputs to a correlated double sampling (CDS) circuit, a programmable offset adjusted and
gain controlled amplifier, a 12-bit analog-to-digital converter.
CDS or S&H (sample and hold) of operation modes can be chosen. The device configuration is
programmed via 3-wire or 4-wired interface, operation modes, offset and gain value of each channel
can be programmed.
2. FEATURES
12-bit A/D Converter
No Missing Code Guaranteed
Three channels analog input with clamp circuit individually
Integrated Correlated Double Sampler (CDS)
Supports Contact Image Sensors (CIS)
Accept CCD/CIS sensor with three channel or single channel analog out
External offset voltage input for CIS reference voltage
Built-in bandgap reference circuit for CDS mode and A/D Converter
Integrated 6-bit Programmable Gain Amplifier (PGA) with 3-channel register selected
Integrated 8-bit offset adjustment with 3-channel register selected
3 MHz sampling rate of offset/gain adjustment circuit
Three-wired or four-wired Serial Interface programmable
Registers readback capability
Low power CMOS device
Power down mode supported
3/5V digital I/O pin
Packageed in 48-pin QFP
Applications:
Flatbed Scanners
Sheetfeed Scanners
Film Scanners
Publication Release Date: December 1998
- 1 - Revision A1









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W6662CF Даташит, Описание, Даташиты
3. PIN CONFIGURATION
Preliminary W6662CF
VRDC
VREF
VINR
AVSS
VING
AVSS
VINB
AVSS
NC
AVDD
CISREF
PAOUT
48 47 46 45 44 43 42 41 40 39 38 37
1 36
2 35
3 34
4 33
5 32
6 31
7 30
8 29
9 28
10 27
11 26
12 25
13 14 15 16 17 18 19 20 21 22 23 24
NC
AVSS
DOUT8
DOUT7
DOUT6
DOUT5
DOUT4
DOUT3
DOUT2
DOUT1
DOUT0
SEN
Fig. 3-1 Pin Assignments.
4. BLOCK DIAGRAM
CISREF
VREF VRDC VRDB VRDT
VINR
Clamp
Bandgap Reference Circuit
CDS
MUX
CDS
Process
Gain/Offset
Adjust
12-bit
ADC
OEN
DOUT[11:0]
VING
Clamp
VINB
Clamp
I/P MUX
Ctrl
Configuration
Register
MUX
R
G
B
DAC
MUX
R
G
B
Weak
Drive
Serial
I/O port
control
CDSCK1 CDSCK2 SEL0 SEL1
Gain Offset
Registers Registers
ADCCLK
Fig. 4 The Block Diagram of W6662 Device.
PAOUT
PAOUTN
SCLK
SEN
SDI/SDIO
SDO/SMS
-2-









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W6662CF Даташит, Описание, Даташиты
Preliminary W6662CF
5. PIN DESCRIPTIONS
PIN NAME TYPE
DESCRIPTION
10, 37, 44
AVDD
AP Analog Power Supply.
4, 6, 8, 35, 42 AVSS
AP Analog Ground.
45, 46
VRDT
AO Voltage Reference Decoupling (Top).
47, 48
VRDB
AO Voltage Reference Decoupling (Bottom).
1
VRDC
AO Voltage Reference Decoupling (Center).
2
VREF
AO Internal Reference Output.
3
VINR
AI Analog Input, Red Channel.
5
VING
AI Analog Input, Green Channel.
7
VINB
AI Analog Input, Blue Channel.
11
CISREF
AI Reference Voltage Input when CIS input.
12
PAOUT
AO PGA Output, low speed analog monitor output for test only.
13 PAOUTN AO PGA Output (negative), low speed analog monitor output for
test only.
14
CDSCK1
DI CDS Clock 1 (Schmitt Trigger Input), Reset Level Sampling
Clock.
15
CDSCK2
DI CDS Clock 2 (Schmitt Trigger Input), Data Level Sampling
Clock.
16
ADCCLK
DI A/D Converter Sampling Clock (Schmitt Trigger Input).
19
DRVDD
DP Digital Driver Power Supply.
17
DRVSS
DP Digital Driver Ground.
20
SEL0
DI Channel Select bit 0.
21
SEL1
DI Channel Select bit 1.
22
SCLK
DI Clock Input of Serial Interface (Schmitt Trigger Input).
23 SDI/SDIO DI/DO Serial Interface of Data Input or Serial Interface of Data
Input/Output.
24 SDO/SMS DI, DO Serial Interface of Data Output, Serial Interface Mode
Select.
25
SEN
DI Enable Signal of Serial Interface, Active Low.
26:34
DOUT[0:8] DO Data Output Bit, DOUT0 is LSB.
38:40
DOUT[9:11] DO Data Output Bit, DOUT11 is MSB.
41
OEN
DI Output Enable, Active Low.
Type: AP is Analog Power, AI is Analog Input, AO is Analog Output, DP is Digital Power, DI is Digital Input, DO is Digital
Output.
Publication Release Date: December 1998
- 3 - Revision A1










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