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W78C801 PDF даташит

Спецификация W78C801 изготовлена ​​​​«Winbond» и имеет функцию, называемую «8-BIT MICROCONTROLLER».

Детали детали

Номер произв W78C801
Описание 8-BIT MICROCONTROLLER
Производители Winbond
логотип Winbond логотип 

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W78C801 Даташит, Описание, Даташиты
W78C801
8-BIT MICROCONTROLLER
GENERAL DESCRIPTION
The W78C801 is an 8-bit microcontroller which can accommodate a wide frequency range with low
power consumption. The instruction set for the W78C801 is fully compatible with the standard 8051.
The W78C801 contains an 4K bytes Mask ROM; a 256 bytes RAM; four 8-bit bi-directional and bit-
addressable I/O ports; an additional 6-bit I/O port P4; two 16-bit timer/counters; a hardware watchdog
timer. These peripherals are supported by a twelve sources two-level interrupt capability. The
W78C801 does not contain serial port.
The W78C801 microcontroller has two power reduction modes, idle mode and power-down mode,
both of which are software selectable. The idle mode turns off the processor clock but allows for
continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.
FEATURES
Fully static design 8-bit CMOS microcontroller
DC-40 MHz operation
256 bytes of on-chip scratchpad RAM
4 KB Mask-ROM
64 KB program memory address space
64 KB data memory address space
Four 8-bit bi-directional ports
Two 16-bit timer/counters
Watchdog Timer
Direct LED drive outputs
Twelve sources, two-level interrupt capability
Wake-up via external interrupts at Port 1
EMI reduction mode
Built-in power management
Code protection mechanism
Packages:
DIP 40: W78C801-24/40
PLCC 44: W78C801P-24/40
PQFP 44: W78C801F-24/40
Publication Release Date: February 1999
- 1 - Revision A3









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W78C801 Даташит, Описание, Даташиты
W78C801
PIN CONFIGURATIONS
40-Pin DIP (W78C801)
INT2, P1.0
INT3, P1.1
INT4,P1.2
INT5,P1.3
INT6,P1.4
INT7,P1.5
INT8,P1.6
INT9,P1.7
RST
P3.0
P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
WR, P3.6
RD, P3.7
XTAL2
XTAL1
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 VDD
39 P0.0, AD0
38 P0.1, AD1
37 P0.2, AD2
36 P0.3, AD3
35 P0.4, AD4
34 P0.5, AD5
33 P0.6, AD6
32 P0.7, AD7
31 EA
30 ALE,P4.5
29 PSEN,P4.6
28 P2.7, A15
27 P2.6, A14
26 P2.5, A13
25 P2.4, A12
24 P2.3, A11
23 P2.2, A10
22 P2.1, A9
21 P2.0, A8
44-Pin PLCC (W78C801P)
44-Pin QFP (W78C801F)
II
NN
TT
,6
5
,
PP
11
..
43
I II
NN N
TT T
43 2
,,,
P PP
1 11
. ..
2 10
P
4V
.D
2D
AAA
DDD
012
,,,
PPP
000
...
012
A
D
3
,
P
0
.
3
INT7,P1.5
INT8,P1.6
INT9,P1.7
RST
P3.0
P4.3
P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
6 5 4 3 2 1 44 43 42 41 40
7 39
8 38
9 37
10 36
11 35
12 34
13 33
14 32
15 31
16 30
17 29
18 19 20 21 22 23 24 25 26 27 28
PP XX VPPP P P P
33 TTS4 22 2 2 2
. . AAS. . . . . .
67 LL 001 2 3 4
, , 21
,, , , ,
/ / AA A A A
WR
89 1 1 1
RD
012
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
P4.1
ALE,P4.5
PSEN,P4.6
P2.7, A15
P2.6, A14
P2.5, A13
INT7,P1.5
INT8,P1.6
INT9,P1.7
RST
P3.0
P4.3
P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
II
NN
TT
,6
5
,
PP
11
..
43
II I
NN N
TT T
,4 3, ,2
P PP
1 11
. ..
2 10
P
4V
.D
2D
AA
DD
01
,,
PP
00
..
01
AA
DD
23
,,
PP
00
..
23
44 43 42 41 40 39 38 37 36 35 34
1 33
2 32
3 31
4 30
5 29
6 28
7 27
8 26
9 25
10 24
11 23
12 13 14 15 16 17 18 19 20 21 22
PP X X V PPP P P P
33 TTS422 2 2 2
. . AAS. . . . . .
67 L L 001 2 3 4
, , 21
,, , , ,
/ / AA A A A
WR
89 1 1 1
RD
0 12
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
P4.1
ALE,P4.5
PSEN,P4.6
P2.7, A15
P2.6, A14
P2.5, A13
-2-









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W78C801 Даташит, Описание, Даташиты
W78C801
PIN DESCRIPTION
SYMBOL
DESCRIPTIONS
EA EXTERNAL ACCESS ENABLE: This pin forces the processor to execute out of
external ROM. It should be kept high to access internal ROM. The ROM address and
data will not be presented on the bus if EA pin is high and the program counter is
within on-chip ROM area. Otherwise they will be presented on the bus.
PSEN
PROGRAM STORE ENABLE: PSEN enables the external ROM data onto the Port 0
address/ data bus during fetch and MOVC operations. When internal ROM access is
performed, no PSEN strobe signal outputs from this pin. This pin also serves the
alternative function P4.6.
ALE ADDRESS LATCH ENABLE: ALE is used to enable the address latch that separates
the address from the data on Port 0. This pin also serves the alternative function P4.5
RST
RESET: A high on this pin for two machine cycles while the oscillator is running resets
the device.
XTAL1 CRYSTAL1: This is the crystal oscillator input. This pin may be driven by an external
clock.
XTAL2 CRYSTAL2: This is the crystal oscillator output. It is the inversion of XTAL1.
VSS GROUND: Ground potential
VDD POWER SUPPLY: Supply voltage for operation.
P0.0P0.7 PORT 0: Port 0 is a bi-directional I/O port which also provides a multiplexed low order
address/data bus during accesses to external memory. The pins of Port 0 can be
individually configured to open-drain or standard port with internal pull-ups.
P1.0P1.7 PORT 1: Port 1 is a bi-directional I/O port with internal pull-ups. The bits have alternate
functions which are described below:
INT2INT9(P1.0P1.7): External interrupt 2 to 9
P2.0P2.7 PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also provides
the upper address bits for accesses to external memory.
P3.0P3.7 PORT 3: Port 3 is a bi-directional I/O port with internal pull-ups. The pins P3.4 to P3.7
can be configured with high sink current which can drive LED displays directly. All bits
have alternate functions, which are described below:
INT0 (P3.2) : External Interrupt 0
INT1(P3.3) : External Interrupt 1
T0(P3.4) : Timer 0 External Input
T1(P3.5) : Timer 1 External Input
WR (P3.6) : External Data Memory Write Strobe
RD (P3.7) : External Data Memory Read Strobe
P4.0P4.6 PORT 4: A 6-bit bi-directional I/O port which is bit-addressable. Pins P4.0 to P4.3 are
available on 44-pin PLCC/QFP package. Pins P4.5 and P4.6 are the alternative
function corresponding to ALE and PSEN.
Publication Release Date: February 1999
- 3 - Revision A3










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