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W78E51BP-40 PDF даташит

Спецификация W78E51BP-40 изготовлена ​​​​«Winbond» и имеет функцию, называемую «8-BIT MTP MICROCONTROLLER».

Детали детали

Номер произв W78E51BP-40
Описание 8-BIT MTP MICROCONTROLLER
Производители Winbond
логотип Winbond логотип 

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W78E51BP-40 Даташит, Описание, Даташиты
Preliminary W78E51B
8-BIT MTP MICROCONTROLLER
GENERAL DESCRIPTION
The W78E51B is an 8-bit microcontroller which can accommodate a wider frequency range with low
power consumption. The instruction set for the W78E51B is fully compatible with the standard 8051.
The W78E51B contains an 4K bytes MTP ROM (Multiple-Time Programmable ROM); a 128 bytes
RAM; four 8-bit bi-directional and bit-addressable I/O ports; an additional 4-bit I/O port P4; two 16-bit
timer/counters; a hardware watchdog timer and a serial port. These peripherals are supported by
seven sources two-level interrupt capability. To facilitate programming and verification, the MTP-
ROM inside the W78E51B allows the program memory to be programmed and read electronically.
Once the code is confirmed, the user can protect the code for security.
The W78E51B microcontroller has two power reduction modes, idle mode and power-down mode,
both of which are software selectable. The idle mode turns off the processor clock but allows for
continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.
FEATURES
Fully static design 8-bit CMOS microcontroller
Wide supply voltage of 4.5V to 5.5V
128 bytes of on-chip scratchpad RAM
4 KB electrically erasable/programmable MTP-ROM
64 KB program memory address space
64 KB data memory address space
Four 8-bit bi-directional ports
One extra 4-bit bit-addressable I/O port, additional INT2 / INT3
(available on 44-pin PLCC/QFP package)
Two 16-bit timer/counters
One full duplex serial port(UART)
Watchdog Timer
seven sources, two-level interrupt capability
EMI reduction mode
Built-in power management
Code protection mechanism
Packages:
DIP 40: W78E51B-24/40
PLCC 44: W78E51BP-24/40
PQFP 44: W78E51BF-24/40
Publication Release Date: December 1998
- 1 - Revision A1









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W78E51BP-40 Даташит, Описание, Даташиты
Preliminary W78E51B
PIN CONFIGURATIONS
40-Pin DIP (W78E51B)
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
RXD, P3.0
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
WR, P3.6
RD, P3.7
XTAL2
XTAL1
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 VDD
39 P0.0, AD0
38 P0.1, AD1
37 P0.2, AD2
36 P0.3, AD3
35 P0.4, AD4
34 P0.5, AD5
33 P0.6, AD6
32 P0.7, AD7
31 EA
30 ALE
29 PSEN
28 P2.7, A15
27 P2.6, A14
26 P2.5, A13
25 P2.4, A12
24 P2.3, A11
23 P2.2, A10
22 P2.1, A9
21 P2.0, A8
44-Pin PLCC (W78E51BP)
P1.5
P1.6
P1.7
RST
RXD, P3.0
INT2, P4.3
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
/
I
N AAAA
T DDDD
3 0123
, ,,,,
P P P PP P PP PP
1 1 1 11 4V 0 0 0 0
. . . . . . D. . . .
4 3 2 10 2D01 23
6 5 4 3 2 1 44 43 42 41 40
7 39
8 38
9 37
10 36
11 35
12 34
13 33
14 32
15 31
16 30
17 29
18 19 20 21 22 23 24 25 26 27 28
PP X XVPPP P P P
33 TTS4 22 2 2 2
. . AAS. . . . . .
67 L L 001 2 3 4
, , 21
,, , , ,
/ / AA A A A
WR
89 1 1 1
RD
012
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
P4.1
ALE
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
44-Pin QFP (W78E51BF)
/
I
N AAAA
T DDDD
3 0123
, ,,,,
P P P PP P PP P P
1 1 1 11 4V 00 0 0
. . . . . . D. . . .
4 3 2 10 2D 01 2 3
P1.5
P1.6
P1.7
RST
RXD, P3.0
INT2, P4.3
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
44 43 42 41 40 39 38 37 36 35 34
1 33
2 32
3 31
4 30
5 29
6 28
7 27
8 26
9 25
10 24
11 23
12 13 14 15 16 17 18 19 20 21 22
PP X X V PPP P P P
33 TTS422 2 2 2
. . AAS. . . . . .
67 L L 001 2 3 4
, , 21
,, , , ,
/ / AA A A A
WR
89 1 1 1
RD
0 12
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
P4.1
ALE
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
-2-









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W78E51BP-40 Даташит, Описание, Даташиты
Preliminary W78E51B
PIN DESCRIPTION
SYMBOL
DESCRIPTIONS
EA EXTERNAL ACCESS ENABLE: This pin forces the processor to execute out of
external ROM. It should be kept high to access internal ROM. The ROM address and
data will not be presented on the bus if EA pin is high and the program counter is
within on-chip ROM area.
PSEN
PROGRAM STORE ENABLE: PSEN enables the external ROM data onto the Port 0
address/ data bus during fetch and MOVC operations. When internal ROM access is
performed, no PSEN strobe signal outputs from this pin.
ALE ADDRESS LATCH ENABLE: ALE is used to enable the address latch that separates
the address from the data on Port 0.
RST
RESET: A high on this pin for two machine cycles while the oscillator is running resets
the device.
XTAL1 CRYSTAL1: This is the crystal oscillator input. This pin may be driven by an external
clock.
XTAL2 CRYSTAL2: This is the crystal oscillator output. It is the inversion of XTAL1.
VSS GROUND: Ground potential
VDD POWER SUPPLY: Supply voltage for operation.
P0.0P0.7 PORT 0: Port 0 is a bi-directional I/O port which also provides a multiplexed low order
address/data bus during accesses to external memory. The pins of Port 0 can be
individually configured to open-drain or standard port with internal pull-ups.
P1.0P1.7 PORT 1: Port 1 is a bi-directional I/O port with internal pull-ups. The bits have alternate
functions which are described below:
T2(P1.0): Timer/Counter 2 external count input
T2EX(P1.1): Timer/Counter 2 Reload/Capture control
P2.0P2.7 PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also provides
the upper address bits for accesses to external memory.
P3.0P3.7 PORT 3: Port 3 is a bi-directional I/O port with internal pull-ups. All bits have alternate
functions, which are described below:
RXD(P3.0) : Serial Port receiver input
TXD(P3.1) : Serial Port transmitter output
INT0 (P3.2) : External Interrupt 0
INT1(P3.3) : External Interrupt 1
T0(P3.4) : Timer 0 External Input
T1(P3.5) : Timer 1 External Input
WR (P3.6) : External Data Memory Write Strobe
RD (P3.7) : External Data Memory Read Strobe
P4.0P4.3 PORT 4: Another bit-addressable bidirectional I/O port P4. P4.3 and P4.2 are
alternative function pins. It can be used as general I/O port or external interrupt input
sources (INT2 / INT3 ).
Publication Release Date: December 1998
- 3 - Revision A1










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