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PDF W78LE51-24 Data sheet ( Hoja de datos )
| Número de pieza | W78LE51-24 | |
| Descripción | 8-BIT MTP MICROCONTROLLER | |
| Fabricantes | Winbond | |
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Preliminary W78LE51
8-BIT MTP MICROCONTROLLER
GENERAL DESCRIPTION
The W78LE51 is an 8-bit microcontroller which can accommodate a wide supply voltage range with
low power consumption. The instruction set for the W78LE51 is fully compatible with the standard
8051. The W78LE51 contains an 4K bytes MTP ROM (Multiple-Time Programmable ROM); a 128
bytes RAM; four 8-bit bi-directional and bit-addressable I/O ports; an additional 4-bit I/O port P4; two
16-bit timer/counters; a hardware watchdog timer and a serial port. These peripherals are supported
by seven sources two-level interrupt capability. To facilitate programming and verification, the MTP-
ROM inside the W78LE51 allows the program memory to be programmed and read electronically.
Once the code is confirmed, the user can protect the code for security.
The W78LE51 microcontroller has two power reduction modes, idle mode and power-down mode,
both of which are software selectable. The idle mode turns off the processor clock but allows for
continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.
FEATURES
• Fully static design 8-bit CMOS microcontroller
• Wide supply voltage of 2.4V to 5.5V
• 128 bytes of on-chip scratchpad RAM
• 4 KB electrically erasable/programmable MTP-ROM
• 64 KB program memory address space
• 64 KB data memory address space
• Four 8-bit bi-directional ports
• One extra 4-bit bit-addressable I/O port, additional INT2 / INT3
(available on 44-pin PLCC/QFP package)
• Two 16-bit timer/counters
• One full duplex serial port(UART)
• Watchdog Timer
• seven sources, two-level interrupt capability
• EMI reduction mode
• Built-in power management
• Code protection mechanism
• Packages:
− DIP 40: W78LE51-24
− PLCC 44: W78LE51P-24
− PQFP 44: W78LE51F-24
Publication Release Date: December 1998
- 1 - Revision A1
1 page  
Preliminary W78LE51
addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To set/clear
bits in the XICON register, one can use the "SETB (/CLR) bit" instruction. For example, "SETB 0C2H"
sets the EX2 bit of XICON.
XICON - external interrupt control (C0H)
PX3 EX3 IE3
IT3 PX2 EX2 IE2
IT2
PX3: External interrupt 3 priority high if set
EX3: External interrupt 3 enable if set
IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced
IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software
PX2: External interrupt 2 priority high if set
EX2: External interrupt 2 enable if set
IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced
IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software
Eight-source interrupt informations:
INTERRUPT
SOURCE
External Interrupt 0
Timer/Counter 0
External Interrupt 1
Timer/Counter 1
Serial Port
External Interrupt 2
External Interrupt 3
VECTOR
ADDRESS
03H
0BH
13H
1BH
23H
33H
3BH
POLLING
SEQUENCE WITHIN
PRIORITY LEVEL
0 (highest)
1
2
3
4
5
6 (lowest)
ENABLE
REQUIRED
SETTINGS
IE.0
IE.1
IE.2
IE.3
IE.4
XICON.2
XICON.6
INTERRUPT
TYPE
EDGE/LEVEL
TCON.0
-
TCON.2
-
-
XICON.0
XICON.3
2. PORT4
Another bit-addressable port P4 is also available and only 4 bits (P4<3:0>) can be used. This port
address is located at 0D8H with the same function as that of port P1, except the P4.3 and P4.2 are
alternative function pins. It can be used as general I/O pins or external interrupt input sources (INT2 ,
INT3 ).
Example:
P4 REG 0D8H
MOV P4, #0AH ; Output data "A" through P4.0−P4.3.
MOV A, P4
; Read P4 status to Accumulator.
SETB P4.0
; Set bit P4.0
CLR P4.1
; Clear bit P4.1
3. Reduce EMI Emission
Because of on-chip MTP-ROM, when a program is running in internal ROM space, the ALE will be
unused. The transition of ALE will cause noise, so it can be turned off to reduce the EMI emission if it
Publication Release Date: December 1998
- 5 - Revision A1
5 Page 
Preliminary W78LE51
Lock bit
This bit is used to protect the customer's program code in the W78LE51. It may be set after the
programmer finishes the programming and verifies sequence. Once this bit is set to logic 0, both the
MTP ROM data and Special Setting Registers can not be accessed again.
MOVC Inhibit
This bit is used to restrict the accessible region of the MOVC instruction. It can prevent the MOVC
instruction in external program memory from reading the internal program code. When this bit is set
to logic 0, a MOVC instruction in external program memory space will be able to access code only in
the external memory, not in the internal memory. A MOVC instruction in internal program memory
space will always be able to access the ROM data in both internal and external memory. If this bit is
logic 1, there are no restrictions on the MOVC instruction.
Encryption
This bit is used to enable/disable the encryption logic for code protection. Once encryption feature is
enabled, the data presented on port 0 will be encoded via encryption logic. Only whole chip erase will
reset this bit.
+5V +5V
A0 to A7
VIL
VIL
VIL
VIL
VIL
VIH
P1
P3.0
P3.1
P3.2
P3.3
P3.6
P3.7
X'tal1
X'tal2
Vss
VDD
P0
EA/Vpp
ALE
RST
PSEN
P2
PGM DATA
VCP
VIL
VIH
VIH
A8 to A15
A0 to A7
VIL
VIL
VIL
VIL
VIH
VIL
P1
P3.0
P3.1
P3.2
P3.3
P3.6
P3.7
X'tal1
X'tal2
Vss
VDD
P0
EA/Vpp
ALE
RST
PSEN
P2
PGM DATA
VCP
VIL
VIH
VIH
A8 to A15
Programming Configuration
Programming Verification
ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Power Supply
Input Voltage
Operating Temperature
Storage Temperature
SYMBOL
VDD−VSS
VIN
TA
TST
MIN.
-0.3
VSS -0.3
0
-55
MAX.
+7.0
VDD +0.3
70
+150
UNIT
V
V
°C
°C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.
- 11 -
Publication Release Date: December 1998
Revision A1
11 Page | ||
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