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W83194BR-138 Datasheet Download - Winbond

Номер произв W83194BR-138
Описание 200MHZ CLOCK FOR SOLANO CHIPSET
Производители Winbond
логотип Winbond логотип 

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W83194BR-138 Даташит, Описание, Даташиты
W83194BR-138
200MHZ CLOCK FOR SOLANO CHIPSET
1.0 GENERAL DESCRIPTION
The W83194BR-138 is a Clock Synthesizer for Intel 815 Solano chipset. W83194BR-138 provides all
clocks required for high-speed RISC or CISC microprocessor and also provides 64 different
frequencies of CPU, SDRAM, PCI, 3V66, IOAPIC clocks frequency setting. All clocks are externally
selectable with smooth transitions.
The W83194BR-138 provides I2C serial bus interface to program the registers to enable or disable
each clock outputs and provides 0.25% and 0.5% center type spread spectrum to reduce EMI.
The W83194BR-138 provides stepless frequency programming by controlling the VCO freq. and the
clock output divisor ratio. Also the skew of CPU, SDRAM and 3V66 clock outputs are programmable.
A watch dog timer is quipped and when time out, the RESET# pin will output 4ms pulse signal.
The W83194BR-138 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.
High drive PCI and SDRAM CLOCK outputs typically provide greater than 1 V /ns slew rate into 30
pF loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as
maintaining 50± 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz provide
better than 0.5V /ns slew rate.
2.0PRODUCT FEATURES
2 CPU clocks
3 3V66 clocks
9 SDRAM clocks for 2 DIMMs
8 PCI synchronous clocks.
Optional single or mixed supply:
(VDDR = VDDP=VDDS = VDD48 = VDD3 = 3.3V, VDDA=VDDC=2.5V)
Skew form CPU to PCI clock -1 to 4 ns, center 2.6 ns
Smooth frequency switch with selections from 66.8 to 200MHz
I2C 2-Wire serial interface and I2C read back
0.25% or 0.5% center type spread spectrum
Programmable registers to enable/stop each output and select modes
(mode as Tri-state or Normal )
48 MHz for USB
24 MHz for super I/O
Packaged in 48-pin SSOP
Publication Release Date: May 2000
- 1 - Revision 0.37







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W83194BR-138 Даташит, Описание, Даташиты
W83194BR-138
PRELIMINARY
3.0 PIN CONFIGURATION
REF1/*SEL24_48#
VDDR
Xin
Xout
VSS
VSS
3V66-0
3V66-1
3V66-2
VDD3
VDDP
PCICLK0/ FS0*
PCICLK1/ FS1&
VSS
PCICLK2/Mode1*
PCICLK3
PCICLK4
VDDP
PCICLK5
PCICLK6
VSS
PD*#/RESET$
SDCLK*
SDATA*
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
*: pull up
&: pull down
$: open drain
^:1.5X~2X driving strength
48 VddA
47 IOAPIC
46 VDDC
45 CPUCLK0
44 CPUCLK1
43 VSS
42 VSS
41 SDRAM 0
40 SDRAM 1
39 SDRAM 2
38 VDDS
37 SDRAM 3
36 SDRAM 4
35 SDRAM 5
34 VSS
33 SDRAM 6
32 SDRAM 7
31 SDRAM_F
30 VDDS
29 VSS
28 24_48MHz/ FS2&
27 48MHz-1/FS3*
26 48MHz-0/ FS4*
25 VDD48
4.0 PIN DESCRIPTION
IN - Input
OUT - Output
I/O - Bi-directional Pin
# - Active Low
* - Internal 250kpull-up
-2-
Publication Release Date: May 2000
Revision 0.37







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W83194BR-138 Даташит, Описание, Даташиты
W83194BR-138
PRELIMINARY
4.1 Crystal I/O
SYMBOL
Xin
Xout
PIN I/O
FUNCTION
3 IN Crystal input with internal loading capacitors(36pF)
and feedback resistors.
4 OUT Crystal output at 14.318MHz nominally with internal
loading capacitors(36pF).
4.2 CPU, SDRAM, PCI, IOAPIC Clock Outputs
SYMBOL
PIN I/O
FUNCTION
CPUCLK [0:1]
45,44
OUT Low skew (< 250ps) clock outputs for host
frequencies such as CPU and Chipset.
PD#/ RESET$
22 I/OD If Mode1*=1, Power Down mode when driven low.
If Mode1*=0, 4ms pulse RESET# (open drain) when
Watch dog timer time out
IOAPIC
47 OUT Clock outputs synchronous with PCI clock and
powered by VddA.
SDRAM_F,
SDRAM[0:7]
31,32,33,35,36 OUT SDRAM clock outputs.
,37,39,40,41
PCICLK0/ *FS0
12 I/O 3.3V 33MHz PCI clock during normal operation.
Latched input for FS0 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks(Default=1).
PCICLK1/ FS1&
13 I/O Low skew (< 250ps) PCI clock outputs.
Latched input for FS1 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks(Default=0).
PCICLK2/ Mode1*
15 I/O Low skew (< 250ps) PCI clock outputs.
Latched input for Mode1* pin at initial power up for
the output PD#/RESET# output selection.
PCICLK [ 3:6 ]
16,17,19,20 OUT Low skew (< 250ps) PCI clock outputs.
3V66 [0:2]
7,8,9
OUT 3.3V output clocks for the chipset.
Publication Release Date: May 2000
- 3 - Revision 0.37










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