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W83194R PDF даташит

Спецификация W83194R изготовлена ​​​​«Winbond» и имеет функцию, называемую «166MHZ CLOCK FOR SIS CHIPSET».

Детали детали

Номер произв W83194R
Описание 166MHZ CLOCK FOR SIS CHIPSET
Производители Winbond
логотип Winbond логотип 

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W83194R Даташит, Описание, Даташиты
W83194R-630A
166MHZ CLOCK FOR SIS CHIPSET
1. GENERAL DESCRIPTION
The W83194R-630A is a Clock Synthesizer for SiS 540/630 chipset. W83194R-630A provides all
clocks required for high-speed RISC or CISC microprocessor such as AMD,Cyrix,Intel Pentium,
Pentium II and also provides 16 different frequencies of CPU clocks frequency setting. All clocks are
externally selectable with smooth transitions. The W83194R-630A makes SDRAM in synchronous or
asynchronous frequency with CPU clocks.
The W83194R-630A provides I2C serial bus interface to program the registers to enable or disable
each clock outputs and W83194R-630A provides the 0.5%, 0.75% center type and 0~0.5% down type
spread spectrum to reduce EMI.
The W83194R-630A accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.
High drive PCI and SDRAM CLOCK outputs typically provide greater than 1 V /ns slew rate into 30
pF loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as
maintaining 50± 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz provide
better than 0.5V /ns slew rate.
2. PRODUCT FEATURES
Supports Pentium, PentiumII, AMD and Cyrix CPUs with I2C.
3 CPU clocks
14 SDRAM clocks for 3 DIMMs
7 PCI synchronous clocks.
Optional single or mixed supply:
(All Vdd = 3.3V) or (Other s Vdd = 3.3V, VddLCPU=2.5V)
Skew form CPU to PCI clock 1 to 4 ns, center 2.6 ns
SDRAM frequency synchronous or asynchronous to CPU clocks
Smooth frequency switch with selections from 66 to 166mhz
I2C 2-Wire serial interface and I2C read back
0.5%, 0.75%center type, 0~0.5% down type spread spectrum to reduce EMI
Programmable registers to enable/stop each output and select modes
(mode as Tri-state or Normal )
48 MHz for USB
24 MHz for super I/O
Packaged in 48-pin SSOP
Publication Release Date: Nov. 1999
- 1 - Revision 0.65









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W83194R Даташит, Описание, Даташиты
W83194R-630A
3. BLOCK DIAGRAM
PLL2
¡Ò2
Xin
Xout
*FS(0:3) 4
*MODE
SEL3.3_2.5#
CPU_STOP#
PCI_STOP#
PD#
*SDATA
*SCLK
XTAL
OSC
PLL1
Spread
Spectrum
STOP
CPU_STOP#
LATCH
POR
5
PCI
clock STOP
Divder
Control
Logic
Config.
Reg.
PCI_STOP#
PRELIMINARY
48MHz
24_48MHz
REF(0:1)
2
CPUCLK(0:2)
3
SDRAM(0:13)
14
PCICLK(0:6)
7
4. PIN CONFIGURATION
Vdd
REF0X2/ *FS3
Vss
Xin
Xout
VddP
PCICLK_F/ *FS1
PCICLK1/ *FS2
PCICLK2/*MODE
Vss
PCICLK3
PCICLK4
PCICLK5
PCICLK6
VddP
Vss
SDRAM 0/CPU_STOP#
SDRAM 1/PCI_STOP#
VddSD
SDRAM 2/PD#
SDRAM 3
Vss
*SDATA
*SDCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 REF1
47 VddLCPU
46 CPUCLK_F
45 CPUCLK0
44 Vss
43 CPUCLK1
42 VddSD
41 SDRAM12
40 SDRAM_F
39 Vss
38 SDRAM11
37 SDRAM 10
36 VddSD
35 SDRAM 9
34 SDRAM 8
33 Vss
32 SDRAM 7
31 SDRAM 6
30 VddSD
29 SDRAM 5
28 SDRAM 4
27 VddSD
26 48MHz/*FS0
25 24_48MHz/SEL2.5_3.3#
Publication Release Date: Nov. 1999
- 2 - Revision 0.65









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W83194R Даташит, Описание, Даташиты
W83194R-630A
5. PIN DESCRIPTION
IN - Input
OUT - Output
I/O - Bi-directional Pin
# - Active Low
* - Internal 250kpull-up
5.1 Crystal I/O
SYMBOL
Xin
PIN
4
Xout
5
PRELIMINARY
I/O
IN
OUT
FUNCTION
Crystal input with internal loading capacitors and
feedback resistors.
Crystal output at 14.318MHz nominally.
5.2 CPU, SDRAM, PCI Clock Outputs
SYMBOL
CPUCLK_F
PIN
46
CPUCLK [ 0:1 ]
SDRAM_F
45,43
40
SDRAM0/CPU_STOP#
17
SDRAM1/PCI_STOP#
18
SDRAM2/PD#
20
SDRAM[3:12]
PCICLK_F/ *FS1
21,28,29,31,32
,34,35,37,38,
41
7
I/O
OUT
OUT
OUT
I/O
I/O
I/O
OUT
I/O
FUNCTION
Low skew (< 250ps) clock outputs for host
frequencies such as CPU, Chipset and Cache.
VddLCPU is the supply voltage for these outputs.
This pin will not be stopped by CPU_STOP#
Low skew (< 250ps) clock outputs for host
frequencies such as CPU, Chipset and Cache.
VddLCPU is the supply voltage for these outputs.
SDRAM clock outputs which have syn. or asyn.
frequencies as CPU clocks.
This pin will not be stopped by CPU_STOP#
SDRAM clock outputs which have syn. or asyn.
frequencies as CPU clocks.
CPU_STOP# input pin when MODE=0.
SDRAM clock outputs which have syn. or asyn.
frequencies as CPU clocks.
PCI_STOP# input pin when MODE=0.
SDRAM clock outputs which have syn. or asyn.
frequencies as CPU clocks.
PD# input pin when MODE=0.
SDRAM clock outputs which have syn. or asyn.
frequencies as CPU clocks.
Latched input for FS1 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks.
Publication Release Date: Nov. 1999
- 3 - Revision 0.65










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