DataSheet26.com

W83194R-17A PDF даташит

Спецификация W83194R-17A изготовлена ​​​​«Winbond» и имеет функцию, называемую «100MHZ AGP CLOCK FOR SIS CHIPSET».

Детали детали

Номер произв W83194R-17A
Описание 100MHZ AGP CLOCK FOR SIS CHIPSET
Производители Winbond
логотип Winbond логотип 

21 Pages
scroll

No Preview Available !

W83194R-17A Даташит, Описание, Даташиты
W83194R-17/-17A
1.0 GENERAL DESCRIPTION
100MHZ AGP CLOCK FOR SIS CHIPSET
The W83194R-17/-17A is a Clock Synthesizer which provides all clocks required for high-speed RISC
or CISC microprocessor such as Intel PentiumII, PentiumPro , AMD or Cyrix. Eight different
frequency of CPU, AGP and PCI clocks are externally selectable with smooth transitions. The
W83194R-17/-17A provides AGP clocks especially for clone chipset. The highest CPU frequency
provided by the W83194R-17 is up to 100MHz, but the one of W83194R-17A is up to 133MHz.
The W83193R-17/-17A provides I2C serial bus interface to program the registers to enable or disable
each clock outputs and choose the 0.5% or 1.5% center type spread spectrum to reduce EMI.
The W83194R-17/-17A accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V
supply. High drive PCI and SDRAM CLOCK outputs typically provide greater than 1 V /ns slew rate
into 30 pF loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads
as maintaining 50¡Ó5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz
provide better than 0.5V /ns slew rate.
2.0 PRODUCT FEATURES
Supports Pentium, PentiumPro, PentiumII, AMD and Cyrix CPUs with I2C.
4 CPU clocks
12 SDRAM clocks for 3 DIMMs
Two AGP clocks
6 PCI synchronous clocks.
Optional single or mixed supply:
(Vdd = Vddq3 = Vddq2 = Vddq2b = 3.3V) or (Vdd =Vddq2 = Vddq3 = 3.3V, Vddq2b = 2.5V)
Skew form CPU to PCI clock -1 to 4 ns, center 2.6 ns, AGP to CPU sync. skew 0 ns (250 ps)
Smooth frequency switch with selections from 60 MHz to 133 MHz CPU
I2C 2-Wire serial interface and I2C read back
¡Ó0.5% or ¡Ó1.5% center type spread spectrum function to reduce EMI
Programmable registers to enable/stop each output and select modes
(mode as Tri-state or Normal )
MODE pin for power Management
48 MHz for USB
24 MHz for super I/O
48-pin SSOP package
Publication Release Date: Sep. 1998
- 1 - Revision 0.20









No Preview Available !

W83194R-17A Даташит, Описание, Даташиты
W83194R-17/-17A
3.0 BLOCK DIAGRAM
PLL2
~
X1 XTAL
X2 OSC
¡Ò2
STOP
FS(0:2) 3
MODE
CPU3.3#_2.5
CPU_STOP#
PCI_STOP#
SDATA
SCLK
PLL1
Spread
Spectrum
LATCH
~
POR
5
Control
Logic
Config.
Reg.
STOP
PCI
clock STOP
Divder
PRELIMINARY
48MHz
24MHz
REF(0:1)
2
AGP(0:1)
2
CPUCLK(0:3)
4
SDRAM(0:11)
12
3
PCICLK(0:4)
5
PCICLK_F
4.0 PIN CONFIGURATION
Vdd
REF0/CPU3.3#_2.5
Vss
Xin
Xout
Vddq3
PCICLK_F/*FS1
PCICLK0/*FS2
Vss
PCICLK1
PCICLK2
PCICLK3
PCICLK4
Vddq3
AGP0
Vss
CPU_STOP#/SDRAM11
PCI_STOP#/SDRAM10
Vddq3
SDRAM 9
SDRAM 8
Vss
SDATA
SDCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
-2-
48 Vddq2
47 AGP1
46 REF1
45 Vss
44 CPUCLK0
43 CPUCLK1
42 Vddq2b
41 CPUCLK2
40 CPUCLK3
39 Vss
38 SDRAM 0
37 SDRAM 1
36 Vddq3
35 SDRAM 2
34 SDRAM 3
33 Vss
32 SDRAM 4
31 SDRAM 5
30 Vddq3
29 SDRAM 6
28 SDRAM 7
27 Vss
26 48MHz/*FS0
25 24MHz/*MODE
Publication Release Date: Sep. 1998
Revision 0.20









No Preview Available !

W83194R-17A Даташит, Описание, Даташиты
W83194R-17/-17A
5.0 PIN DESCRIPTION
IN - Input
OUT - Output
I/O - Bi-directional Pin
# - Active Low
* - Internal 250kpull-up
PRELIMINARY
5.1 Crystal I/O
SYMBOL
Xin
Xout
PIN I/O
FUNCTION
4 IN Crystal input with internal loading capacitors and
feedback resistors.
5 OUT Crystal output at 14.318MHz nominally.
5.2 CPU, SDRAM, PCI Clock Outputs
SYMBOL
CPUCLK [ 0:3 ]
AGP[ 0:1]
SDRAM11/
CPU_STOP#
SDRAM10/
PCI_STOP#
SDRAM [ 0:9]
PCICLK_F/ *FS1
PIN
40,41,43,44
15,47
17
18
20,21,28,29,31
,32,34,
35,37,38
7
I/O
OUT
OUT
I/O
I/O
O
I/O
FUNCTION
Low skew (< 250ps) clock outputs for host
frequencies such as CPU, Chipset and Cache.
Vddq2b is the supply voltage for these outputs.
Accelerate Graphic Port clock outputs
If MODE =1 (default), then this pin is a SDRAM
Clock buffered output. If MODE = 0 , then this pin is
CPU_STOP# input used in power management
mode for synchronously stopping the all CPU clocks.
If MODE = 1 (default), then this pin is a SDRAM
clock output. If MODE = 0 , then this pin is
PCI_STOP # and used in power management mode
for synchronously stopping the all PCI clocks.
SDRAM clock outputs which have the same
frequency as CPU clocks.
Latched input for FS1 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks.
Free running PCI clock during normal operation.
Publication Release Date: Sep. 1998
- 3 - Revision 0.20










Скачать PDF:

[ W83194R-17A.PDF Даташит ]

Номер в каталогеОписаниеПроизводители
W83194R-17100MHZ AGP CLOCK FOR SIS CHIPSETWinbond
Winbond
W83194R-17A100MHZ AGP CLOCK FOR SIS CHIPSETWinbond
Winbond

Номер в каталоге Описание Производители
TL431

100 мА, регулируемый прецизионный шунтирующий регулятор

Unisonic Technologies
Unisonic Technologies
IRF840

8 А, 500 В, N-канальный МОП-транзистор

Vishay
Vishay
LM317

Линейный стабилизатор напряжения, 1,5 А

STMicroelectronics
STMicroelectronics

DataSheet26.com    |    2020    |

  Контакты    |    Поиск