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W83194R-58 PDF даташит

Спецификация W83194R-58 изготовлена ​​​​«Winbond» и имеет функцию, называемую «100 MHZ AGP CLOCK FOR VIA CHIPSET».

Детали детали

Номер произв W83194R-58
Описание 100 MHZ AGP CLOCK FOR VIA CHIPSET
Производители Winbond
логотип Winbond логотип 

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W83194R-58 Даташит, Описание, Даташиты
Preliminary W83194R-37/-58
100 MHZ AGP CLOCK FOR VIA CHIPSET
1.0 GENERAL DESCRIPTION
The W83194R-37/-58 is a Clock Synthesizer for VIA chipset. W83194R-37 provides all clocks
required for high-speed RISC or CISC microprocessor such as Intel PentiumPro, AMD or Cyrix. Eight
different frequencies of CPU, W83194R-58 provides all clocks required for high-speed RISC or CISC
microprocessor such as Intel PentiumII and also provides 16 different frequencies of CPU clocks by
software setting (additional register0 bit2). AGP and PCI clocks are externally selectable with smooth
transitions. The W83194R-37/-58 provides AGP clocks especially for clone chipset, and makes
SDRAM in synchronous frequency with CPU or AGP clocks.
The W83194R-37/-58 provides I2C serial bus interface to program the registers to enable or disable
each clock outputs and choose the 0.25%, 0.5% or 0.5%,1.5% center type spread spectrum to reduce
EMI.
The W83194R-37/-58 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.
High drive PCI and SDRAM CLOCK outputs typically provide greater than 1V /nS slew rate into 30 pF
loads. CPU CLOCK outputs typically provide better than 1V /nS slew rate into 20 pF loads as
maintaining 50 ±5% duty cycle. The fixed frequency outputs as REF, 24 MHz, and 48 MHz provide
better than 0.5V /nS slew rate.
2.0 FEATURES
Supports Pentium, PentiumPro, PentiumII, AMD and Cyrix CPUs with I2C.
4 CPU clocks
12 SDRAM clocks for 3 DIMs
Two AGP clocks
6 PCI synchronous clocks.
Optional single or mixed supply:
(VDD = VDDq3 = VDDq2 = VDDq2b = 3.3V) or (VDD = VDDq3 = VDDq2 = 3.3V, VDDq2b = 2.5V)
Skew form CPU to PCI clock -1 to 4 nS, center 2.6 nS, AGP to CPU sync. skew 0 nS (250 pS)
SDRAM frequency synchronous to CPU or AGP clocks
Smooth frequency switch with selections from 60 to 100 MHz CPU (-37) and 66 to 150 MHz (-58)
I2C 2-Wire serial interface and I2C read back
±0.5% or ±1.5% (-37) and 0.25%, 0.5% (-58) center type spread spectrum to reduce EMI
Programmable registers to enable/stop each output and select modes (mode as Tri-state or Normal)
MODE pin for power Management
48 MHz for USB
24 MHz for super I/O
Packaged in 48-pin SSOP
Publication Release Date: April 1999
- 1 - Revision A1









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W83194R-58 Даташит, Описание, Даташиты
Preliminary W83194R-37/-58
3.0 PIN CONFIGURATION
VDD
* REF0/CPU3.3#_2.5
Vss
Xin
Xout
VDDq3
PCICLK_F/*FS1
PCICLK0/*FS2
Vss
PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDDq3
AGP0
Vss
CPU_STOP#/SDRAM11
PCI_STOP#/SDRAM10
VDDq3
SDRAM 9
SDRAM 8
Vss
SDATA
SDCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 VDDq2
47 AGP1
46 REF1/*SD_SEL#
45 Vss
44 CPUCLK0
43 CPUCLK1
42 VDDq2
41 CbPUCLK2
40 CPUCLK3
39 Vss
38 SDRAM 0
37 SDRAM 1
36 VDDq3
35 SDRAM 2
34 SDRAM 3
33 Vss
32 SDRAM 4
31 SDRAM 5
30 VDDq3
29 SDRAM 6
28 SDRAM 7
27 Vss
26 48MHz/*FS0
25 24MHz/*MODE
4.0 BLOCK DIAGRAM
PLL2
~
X1 XTAL
X2 OSC
¡Ò2
STOP
*FS(0:2) 3
*MODE
CPU3.3#_2.5
*SD_SEL#
CPU_STOP#
PCI_STOP#
*SDATA
*SCLK
PLL1
Spread
Spectrum
STOP
CPU_STOP#
LATCH
~
POR
5
PCI
clock STOP
Divder
Control
Logic
Config.
Reg.
PCI_STOP#
48MHz
24MHz
REF(0:1
2)
AGP(0:1)
2
CPUCLK(0:3)
4
SDRAM(0:11)
12
3
PCICLK(0:4)
5
PCICLK_F
-2-









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W83194R-58 Даташит, Описание, Даташиты
Preliminary W83194R-37/-58
5.0 PIN DESCRIPTION
IN - Input
OUT - Output
I/O - Bi-directional Pin
# - Active Low
* - Internal 250kpull-up
5.1 Crystal I/O
SYMBOL
Xin
PIN
4
Xout
5
I/O FUNCTION
IN Crystal input with internal loading capacitors and feedback
resistors.
OUT Crystal output at 14.318 MHz nominally.
5.2 CPU, SDRAM, PCI Clock Outputs
SYMBOL
CPUCLK [ 0:3 ]
AGP[ 0:1]
SDRAM11/
CPU_STOP#
SDRAM10/
PCI_STOP#
SDRAM [ 0:9]
PCICLK_F/ *FS1
PCICLK 0/ *FS2
PCICLK [ 1:4 ]
PIN
40, 41, 43,
44
15, 47
17
18
20, 21, 28,
29, 31, 32,
34, 35, 37,
38
7
8
10, 11, 12,
13
I/O FUNCTION
OUT Low skew (< 250 pS) clock outputs for host frequencies
such as CPU, Chipset and Cache. VDDq2b is the supply
voltage for these outputs.
OUT Accelerate Graphic Port clock outputs
I/O If MODE = 1 (default), then this pin is a SDRAM clock
buffered output of the crystal. If MODE = 0, then this pin is
CPU_STOP# input used in power management mode for
synchronously stopping the all CPU clocks.
I/O If MODE = 1 (default), then this pin is a SDRAM clock
output. If MODE = 0, then this pin is PCI_STOP # and
used in power management mode for synchronously
stopping the all PCI clocks.
O SDRAM clock outputs which have the same frequency as
CPU clocks.
I/O Latched input for FS1 at initial power up for H/W selecting
the output frequency of CPU, SDRAM and PCI clocks.
Free running PCI clock during normal operation.
I/O Latched input for FS2 at initial power up for H/W selecting
the output frequency of CPU, SDRAM and PCI clocks.
PCI clock during normal operation.
OUT Low skew (< 250 pS) PCI clock outputs.
Publication Release Date: April 1999
- 3 - Revision A1










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