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W83194R-67A PDF даташит

Спецификация W83194R-67A изготовлена ​​​​«Winbond» и имеет функцию, называемую «100MHZ 3-DIMM CLOCK FOR VIA MVP4».

Детали детали

Номер произв W83194R-67A
Описание 100MHZ 3-DIMM CLOCK FOR VIA MVP4
Производители Winbond
логотип Winbond логотип 

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W83194R-67A Даташит, Описание, Даташиты
W83194R-67A
100MHZ 3-DIMM CLOCK FOR VIA MVP4
1.0 GENERAL DESCRIPTION
The W83194R-67A is a Clock Synthesizer which provides all clocks required for high-speed RISC or
CISC microprocessor such as Intel Pentium , AMD and Cyrix. W83194R-67A provides sixteen
CPU/PCI frequencies which are externally selectable with smooth transitions. W83194R-67AA also
provides 13 SDRAM clocks controlled by the none-delay buffer_in pin.
The W83194R-67A accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.
Spread spectrum built in at ¡Ó0.5% or ¡Ó0.25% to reduce EMI. Programmable stopping individual
clock outputs and frequency selection through I2C interface. The device meets the Pentium power-up
stabilization, which requires CPU and PCI clocks be stable within 2 ms after power-up.
High drive six PCI and thirteen SDRAM CLOCK outputs typically provide greater than 1 V /ns slew
rate into 30 pF loads. Two CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20
pF loads as maintaining 50¡Ó 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48
MHz provide better than 0.5V /ns slew rate.
2.0 PRODUCT FEATURES
Supports Pentium, AMD, Cyrix CPU with I2C.
4 CPU clocks (one free-running CPU clock)
13 SDRAM clocks for 3 DIMs
6 PCI synchronous clocks
Optional single or mixed supply:
(Vddq1=Vddq2 = Vddq3 = Vddq4 = VddL1 =VddL2= 3.3V) or (Vddq1= Vddq2 = Vddq3=Vddq4 =
3.3V, VddL1 = VdqL2 = 2.5V)
< 250ps skew among CPU and SDRAM clocks
< 4ns propagation delay SDRAM from buffer input
Skew from CPU(earlier) to PCI clock -1 to 4ns, center 2.6ns.
Smooth frequency switch with selections from 60 MHz to 124 MHz CPU
I2C 2-Wire serial interface and I2C read back
¡Ó0.25% or ¡Ó0.5% spread spectrum function to reduce EMI
Programmable registers to enable/stop each output and select modes
(mode as Tri-state or Normal )
2ms power up clock stable time
MODE pin for power Management
One 48 MHz for USB & one 24 MHz for super I/O
48-pin SSOP package
Publication Release Date: Feb. 1999
- 1 - Revision 0.30









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W83194R-67A Даташит, Описание, Даташиты
W83194R-67A
3.0 BLOCK DIAGRAM
Xin
Xout
BUFFER IN
FS(0:3)* 4
MODE*
*CPU_STOP#
*PCI_STOP#
SDATA*
SDCLK*
PLL2
~
XTAL
OSC
1/2
PLL1
Spread
Spectrum
LATCH
~
POR
4
Control
Logic
Config.
Reg.
STOP
STOP
PCI
Clock STOP
Divider
PRELIMINARY
48MHz
24MHz
REF(0:1)
2
CPUCLK_F
CPUCLK(0:2)
3
SDRAM_F
SDRAM(0:11)
12
PCICLK(0:4)
5
PCICLK_F
4.0 PIN CONFIGURATION
Vddq1
* PCI_STOP#/REF0
Vss
Xin
Xout
Vddq2
PCICLK_F/ *MODE
PCICLK0/ *FS3
Vss
PCICLK1
PCICLK2
PCICLK3
PCICLK4
Vddq2
BUFFER IN
Vss
SDRAM11
SDRAM10
Vddq3
SDRAM 9
SDRAM 8
Vss
*SDATA
*SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 REF1/ *FS2
47 VddL1
46 CPUCLK_F
45 CPUCLK0
44 Vss
43 CPUCLK1
42 CPUCLK2
41 *CPU_STOP#
40 Vss
39 SDRAM_F
38 SDRAM 0
37 SDRAM 1
36 Vddq3
35 SDRAM 2
34 SDRAM 3
33 Vss
32 SDRAM 4
31 SDRAM 5
30 Vddq3
29 SDRAM 6
28 SDRAM 7
27 Vddq4
26 48MHz/ *FS0
25 24MHz/ *FS1
Publication Release Date: Feb. 1999
- 2 - Revision 0.30









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W83194R-67A Даташит, Описание, Даташиты
W83194R-67A
5.0 PIN DESCRIPTION
IN - Input
OUT - Output
I/O - Bi-directional Pin
# - Active Low
* - Internal 250kpull-up
5.1 Crystal I/O
SYMBOL
Xin
Xout
PIN
4
5
PRELIMINARY
I/O
IN
OUT
FUNCTION
Crystal input with internal loading capacitors and
feedback resistors.
Crystal output at 14.318MHz nominally.
5.2 CPU, SDRAM, PCI, IOAPIC Clock Outputs
SYMBOL
CPUCLK_F
CPUCLK[0:2]
*CPU_STOP#
SDRAM_F
SDRAM [ 0:11]
PCICLK_F/
*MODE
PCICLK0/*FS3
PCICLK [ 1:4 ]
BUFFER IN
PIN
46
45,43,42
41
39
17,18,20,21,28
,29,31,32,34,
35,37,38
7
8
10,11,12,13
I/O
OUT
OUT
IN
OUT
OUT
I/O
I/O
OUT
FUNCTION
Free running CPU clock. Not affected by
CPU_STOP#
Low skew (< 250ps) clock outputs for host
frequencies such as CPU, Chipset and Cache.
Powered by VddL2. Low if CPU_STOP# is low.
This asynchronous input halts CPUCLK[0:2] and
SDRAM(0:11) at logic level when driven low.
Free running SDRAM clock. Not affected by
CPU_STOP#
SDRAM clock outputs. Fanout buffer outputs from
BUFFER IN pin.(Controlled by chipset)
Free running PCI clock during normal operation.
Latched Input. Mode=1, Pin 2 is REF0; Mode=0,
Pin2 is PCI_STOP#
Low skew (< 250ps) PCI clock outputs.
Latched input for FS3 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks.
Low skew (< 250ps) PCI clock outputs. Synchronous
to CPU clocks with 1/-4ns skew(CPU early).
15 IN Inputs to fanout for SDRAM outputs.
Publication Release Date: Feb. 1999
- 3 - Revision 0.30










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W83194R-67A100MHZ 3-DIMM CLOCK FOR VIA MVP4Winbond
Winbond
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