даташит W83195BR-25 PDF ( Datasheet )

		
 
	 
No Preview Available !

W83195BR-25
200MHZ 3-DIMM CLOCK FOR SOLANO CHIPSET
1.0 GENERAL DESCRIPTION
The W83195BR-25 is a Clock Synthesizer for Intel 815 Solano chipset. W83195BR-25 provides all
clocks required for high-speed RISC or CISC microprocessor and also provides 64 different
frequencies of CPU, SDRAM, PCI, 3V66, IOAPIC clocks frequency setting. All clocks are externally
selectable with smooth transitions.
The W83195BR-25 provides I2C serial bus interface to program the registers to enable or disable
each clock outputs and provides 0.25% and 0.5% center type spread spectrum to reduce EMI.
The W83195BR-25 provides stepless frequency programming by controlling the VCO freq. and the
clock output divisor ratio. Also skew of CPU,SDRAM and 3V66 clock outputs are programmable. A
watch dog timer is quipped and when time out, the RESET# pin will output 4ms pulse signal.
The W83195BR-25 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.
High drive PCI and SDRAM CLOCK outputs typically provide greater than 1 V /ns slew rate into 30
pF loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as
maintaining 50± 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz provide
better than 0.5V /ns slew rate.
2.0 PRODUCT FEATURES
• 2 CPU clocks (2.5V)
• 3 3V-66 clocks (3.3V)
• 12 SDRAM clocks for 3 DIMMs(3.3V)
• 8 PCI synchronous clocks.
• Optional single or mixed supply:
(VDDR = VDDP=VDDS = VDD48 = VDD3 = 3.3V, VDDA=VDDC=2.5V)
• Skew form CPU to PCI clock -1 to 4 ns, center 2.6 ns
• Smooth frequency switch with selections from 66.8 to 200MHz
• I2C 2-Wire serial interface and I2C read back
• 0.25% center and 0.5% center type spread spectrum
• Programmable registers to enable/stop each output and select modes
(mode as Tri-state or Normal )
• 48 MHz for USB
• 24 MHz for super I/O
• Packaged in 56-pin SSOP
Publication Release Date: May 2000
- 1 - Revision 0.52







 
	 
No Preview Available !

3.0 PIN CONFIGURATION
VDDR
Xin
Xout
VSS
VSS
3V66-0
3V66-1
3V66-2
VDD3
VDDP
PCICLK0/ FS0&
PCICLK1/ *FS1
PCICLK2/SEL24_48*
VSS
PCICLK3^/Mode1*
PCICLK4^
PCICLK5^
VDDP
PCICLK6^
PCICLK7
VSS
PD#/RESET$
*SDCLK
*SDATA
VDDS
SDRAM 11
SDRAM 10
VSS
Note: * Internal pull-up
&: Internal pull-down
^ 1.5~2 strength
$: Open drain
4.0 PIN DESCRIPTION
IN - Input
OUT - Output
I/O - Bi-directional Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
-2-
W83195BR-25
PRELIMINARY
56 REF0/ FS4&^
55 VddA
54 IOAPIC
53 VDDC
52 CPUCLK0
51 CPUCLK1
50 VSS
49 VSS
48 SDRAM 0
47 SDRAM 1
46 SDRAM 2
45 VDDS
44 SDRAM 3
43 SDRAM 4
42 SDRAM 5
41 VSS
40 SDRAM 6
39 SDRAM 7
38 SDRAM_F
37 VDDS
36 VSS
35 24_48MHz/ FS2&
34 48MHz/ *FS3 ^
33 VDD48
32 VDDS
31 SDRAM 8
30 SDRAM 9
29 VSS
Publication Release Date: May 2000
Revision 0.52







 
	 
No Preview Available !

W83195BR-25
# - Active Low
* - Internal 250kΩ pull-up
PRELIMINARY
4.1 Crystal I/O
SYMBOL
Xin
Xout
PIN I/O
FUNCTION
2 IN Crystal input with internal loading capacitors(36pF)
and feedback resistors.
3 OUT Crystal output at 14.318MHz nominally with internal
loading capacitors(36pF).
4.2 CPU, SDRAM, PCI, IOAPIC Clock Outputs
SYMBOL
PIN I/O
FUNCTION
CPUCLK [0:1]
52,51
OUT Low skew (< 250ps) clock outputs for host
frequencies such as CPU and Chipset.
PD#/RESET$
22 IN Mode1*=1, Power Down mode when driven low.
Mode1*=0, RESET# open drain (4ms low active
pulse when Watch Dog time out)
IOAPIC
54 OUT Clock outputs synchronous with PCI clock and
powered by VddA.
SDRAM_F,
SDRAM[0:11]
38, 48,47,46,
44,43,42,40,
39,31, 30,27,
26
OUT SDRAM clock outputs.
PCICLK0/ FS0&
11 I/O 3.3V 33MHz PCI clock during normal operation.
Latched input for FS0 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks(Default=0).
PCICLK1/ *FS1
12 I/O Low skew (< 250ps) PCI clock outputs.
Latched input for FS1 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks(Default=1).
PCICLK2/ *SEL24_48
13
I/O Low skew (< 250ps) PCI clock outputs.
Latched input for SEL24_48 at initial power up for the
output frequency of 24MHz(HIGH) and 48MHz(LOW)
clocks.
PCICLK3/ Mode1*
15 I/O Low skew (< 250ps) PCI clock outputs.
Latched input for Mode* pin at initial power up for the
output PD# /RESET# output selection.
PCICLK [ 4:7 ]
16,17,19,20 OUT Low skew (< 250ps) PCI clock outputs.
3V66 [0:2]
6,7,8
OUT 3.3V output clocks for the chipset.
Publication Release Date: May 2000
- 3 - Revision 0.52