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WARP20 PDF даташит

Спецификация WARP20 изготовлена ​​​​«STMicroelectronics» и имеет функцию, называемую «8-BIT FUZZY CO-PROCESSOR».

Детали детали

Номер произв WARP20
Описание 8-BIT FUZZY CO-PROCESSOR
Производители STMicroelectronics
логотип STMicroelectronics логотип 

28 Pages
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WARP20 Даташит, Описание, Даташиты
W.A.R.P.2.0
8-BIT FUZZY CO-PROCESSOR
PRELIMINARY DATA
Digital Fuzzy Co-processor 8-bit I/O
High Speed Rules Processing
4 Input, 2 Output, 32 Rules in 33.1µs
Up to 256 Rules (4 Antecedents,1 Consequent)
Up to 8 Input Configurable Variables
Up to 16 Membership Functions for an Input
Variable
Antecedent Membership Functions with
Triangular and Trapezoidal Shape
Up to 4 Output Variables
Up to 256 Membership Functions for all
Consequents
Singleton Consequent Membership Functions
Defuzzification on chip
Maximum Clock Frequency 40MHz
A/D Start Convertion Pulse presettable
Direct Interface to all popular microprocessor
Handshaking Signal Polarity presettable
Operates ”STAND ALONE” (without µP) if
desired
Standard +5V Supply Voltage
Software Tools and Emulators Availability
Pin number: 52
68-lead Plastic Leaded Chip Carrier package.
Figure 2. Simplified Block Diagram.
PLCC68
Figure 1. Logic Diagram.
MCLK VSS VDD WAIT
I0-I7
SIS0- SI S2
8
3
LASTIN
OE
AUTO
W.A.R. P.
2.0
12
O0-O11
2
OC 0-O C 1
DS
RD
READY
ENDOFL
ERR OFL PRESET BUSY
8
Input Port
with
HANDSHAKE
ALPHA
CALCULATOR
INFE RE NCE
UNIT
DEFUZZIFIER
8
Ouput Port
with
HANDSHAKE
INTERNAL BUS
ANTECE DENT
MEMORY
P ROGRAM &
CONSE QUENT
MEMORY
P ROGRAMMABLEA/D
OUTPUT PULSE
March 1996
This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without no tice.
1/28









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WARP20 Даташит, Описание, Даташиты
W.A.R.P.2.0
Figure 3. Pin Connections
VSS
VDD
MCLK
PRESET
OFL
AUTO
LASTIN
OE
RD
TEST
DS
ENDOFL
ERR
BUSY
READY
VSS
VDD
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
W.A.R.P. 2.0
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
nc
nc
nc
VDD
VSS
O0
O1
O2
O3
O4
O5
O6
VDD
VSS
nc
nc
nc
Note: nc = Not Connected.
GENERAL DESCRIPTION
W.A.R.P.2.0 is a member of the W.A.R.P. family of
fuzzy microprocessors, completely developed and
produced by SGS-THOMSON Microelectronics us-
ing the high performance, reliable HCMOS4T
(O.7µm) process.
W.A.R.P.2.0 can be used both as a Fuzzy Co-proc-
essor or as a stand-alone microcontroller. In the
former case, it can work together with standard
micros which shall perform normal control tasks
while W.A.R.P.2.0 will be indipendentlyresponsible
for all the fuzzy related computing.
W.A.R.P.2.0 core includes the fuzzifier (ALPHA
calculator), the inference unit, and the defuzzifier.
The I/O capabilities demanded by microprocessor
applications are fulfilled by W.A.R.P.2.0 with 8 Input
and 4 Output lines which can be supported by
handshaking signals.
The capability of preset the polarity of the hand-
shaking signals simplifies the interface with the
host processor.
An internal Start Conversion pulse is provided to
allow simple use for waveform generation which
can be directly applied to drive an A/D converter.
The output 3-STATE buffer can be temporarily
frozen in order to synchronize W.A.R.P.2.0 with
slower devices.
2/28
Running W.A.R.P.2.0 involves a downloading
phase and an On-Line phase. The downloading
phase allows the setting of the processor, in terms
of I/O number, universe of discourse, Membership
Functions (MFs) and rules. During this phase
W.A.R.P.2.0 prepares its internal memories for the
On-Line elaboration phase and loads the micro-
code in its program memory. This microcode, which
drives the On-Line phase, is generated by the
Compiler (see FUZZYSTUDIO2.0 User Man-
ual). After that W.A.R.P.2.0 is ready to run (On-Line
phase) processing inputs and producing the re-
lated outputs according to the configuration loaded
in the downloading phase. It is also possible to
provide the processor with inputs in any order by
specifying their identification numbers.
Two basic memories are available in W.A.R.P.2.0 :
the Antecedent Memory (AM) and the Pro-
gram/Consequent Memory (PCM). The antece-
dent MFs, portrayed by a resolution of 28 elements,
are stored in the AM (256 bytes). W.A.R.P.2.0
exploits a SGS-THOMSON patented strategy to
store the MFs in the AM.
The information about Rules and Consequent MFs
are stored in the PCM (1.4 Kbyte).
FUZZYSTUDIO2.0 is a powerful development
environment consisting of board and software al-
lows an easy configuration and use of W.A.R.P.2.0.









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WARP20 Даташит, Описание, Даташиты
W.A.R.P.2.0
Table 1. Pin Description
Pin Assignment
11,26,31,40,48,57
1,10,25,30,39,47,56
19
12
13
15
65
Name
VDD
VSS
TEST
MCLK
PRESET
AUTO
SIS0
64 SIS1
63 SIS2
67 I0
68 I1
2 I2
3 I3
4 I4
5 I5
6 I6
7 I7
14 OFL
18 RD
16 LASTIN
17 OE
66 WAIT
24 READY
21 ENDOFL
23 BUSY
20 DS
22 ERR
33 OC0
32 OC1
55 O0
54 O1
53 O2
52 O3
51 O4
50 O5
49 O6
38 O7
37 O8
36 O9
35 O10
34 O11
Pins Type
-
-
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Fun ction
Power Supply
Ground
Testing (It must be connected to VSS)
Master Clock (up to 40 MHz)
Preset
Auto/Manual-Boot
Auto-Boot Speed (Ext. Memory Support AccessTime) /
Input Selection bit 0
Auto-Boot Speed (Ext. Memory Support Access Time) /
Input Selection bit 1
Auto-Boot Speed (Ext. Memory Support Access Time) /
Input Selection bit 2
Data Input bit 0
Data Input bit 1
Data Input bit 2
Data Input bit 3
Data Input bit 4
Data Input bit 5
Data Input bit 6
Data Input bit 7
Off-Line/On-Line Switch
Handshaking Read Ready
Last Input (Start Elaboration) bit
Output Enable/3-STATE bit
Temporary Output Processing Stop
Handshaking Output Signal
Offline Phase (external memory downloading) End
Elaboration Phase Indicator
Data Strobe (Output Ready Signal)
Error Flag
Output Identifier bit 0
Output Identifier bit 1
External Memory Address/Defuzzified Output bit 0
External Memory Address/Defuzzified Output bit 1
External Memory Address/Defuzzified Output bit 2
External Memory Address/Defuzzified Output bit 3
External Memory Address/Defuzzified Output bit 4
External Memory Address/Defuzzified Output bit 5
External Memory Address/Defuzzified Output bit 6
External Memory Address/Defuzzified Output bit 7
External Memory Address bit 8 /
Next Input Progressive Number bit 0
External Memory Address bit 9 /
Next Input Progressive Number bit 1
External Memory Address bit 10 /
Next Input Progressive Number bit 2
External Memory Address bit 11 /
Start Conversion for the external A/D
3/28










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