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PDF WM2630 Data sheet ( Hoja de datos )
| Número de pieza | WM2630 | |
| Descripción | Octal 12-bit/ Serial Input/ Voltage Output DAC with Internal Reference | |
| Fabricantes | Wolfson Microelectronics plc | |
| Logotipo |  |
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WM2630
Octal 12-bit, Serial Input, Voltage Output DAC
with Internal Reference
Production Data, February 2001, Rev 1.1
FEATURES
• Eight 12-bit DACs in one package
• Dual supply 2.7V to 5.5V operation
• DNL ±0.5 LSBs, INL ±2.0 LSBs typ.
• Programmable settling time / power
(1.0µs typ. in fast mode)
• Internal programmable Voltage Reference
• Microcontroller compatible Serial Interface
• Power Down Mode ( < 0.1µA)
• Monotonic over Temperature
• Data Output for Daisy Chaining
APPLICATIONS
• Battery powered test instruments
• Digital offset and gain adjustment
• Battery operated / remote industrial controls
• Programmable Loop Controllers
• CNC Machine Tools
• Machine and motion control devices
• Wireless telephone and communication systems
• Robotics
ORDERING INFORMATION
DESCRIPTION
The WM2630 is an octal, 12-bit, resistor string digital-to-
analogue converter. The eight individual DACs contained in the
IC can be switched in pairs between fast and slow (low power)
operation modes, or powered down, under software control.
Alternatively, the whole device can be powered down, reducing
current consumption to less than 0.1µA.
The DAC outputs are buffered by a rail-to-rail amplifier with a
gain of two, which is configurable as Class A (fast mode) or
Class AB (for low-power mode).
The WM2630 has been designed to interface directly to
industry standard microprocessors and DSPs, and can
operate on two separate analogue and digital power supplies. It
is programmed with a 16-bit serial word comprising 4 address
bits and up to 12 DAC or control register data bits. All eight
DACs can be simultaneously forced to a preset value using a
preset input pin.
A daisy-chain data output makes it possible to control several
of Wolfson’s octal DACs from the same interface, without
increasing the number of control lines.
The device is available in a 20-pin TSSOP package.
Commercial temperature (0° to 70°C) and Industrial
temperature (-40° to 85°C) variants are supported.
DEVICE
W M2630CDT
W M2630IDT
TEMP. RANGE
0° to 70°C
-40° to 85°C
PACKAGE
20-pin TSSOP
20-pin TSSOP
BLOCK DIAGRAM
TYPICAL PERFORMANCE
1.024V / 2.048V
SELECTABLE
REFERENCE
DIN (2)
SCLK (3)
FS (4)
MODE (17)
PREB (5)
DOUT (19)
SERIAL
INTERFACE
AND
CONTROL
LOGIC
REF
(16)
AVDD
(11)
DVDD
(20)
DAC A
LATCH
RESISTOR
STRING
POWER/SPEED
CONTROL
REF
DACs B, C, D, E, F, G, H
as DAC A
(12) OUT A
(6-9, 13-15)
OUT B to H
LOADB
(18)
AGND
(10)
DGND
(1)
1
0.75
0.5
0.25
0
-0.25
-0.5
-0.75
-1
0
512
1024
1536
2048
2560
3072
3584
4096
DIGITAL CODE
WOLFSON MICROELECTRONICS LTD
Bernard Terrace, Edinburgh, EH8 9NX, UK
Tel: +44 (0) 131 667 9386
Fax: +44 (0) 131 667 5176
Email: [email protected]
www.wolfsonmicro.co.uk
Production Data datasheets contain final
specifications current on publication date.
Supply of products conforms to Wolfson
Microelectronics’ Terms and Conditions.
©2001 Wolfson Microelectronics Ltd.
1 page  
Production Data
WM2630
Test Characteristics:
RL = 10kΩ, CL = 100pF AVDD = DVDD = 5V ± 10%, VREF = 2.048V and AVDD = DVDD = 3V ± 10%, VREF = 1.024V over
recommended operating free-air temperature range (unless noted otherwise).
PARAMETER
Reference Configured as Input
SYMBOL
TEST
CONDITIONS
MIN TYP
MAX
UNIT
Reference input resistance
RREF
50 kΩ
Reference input capacitance
CREF
10 pF
Reference feedthrough
Reference input bandwidth
Reference Configured as Output
VREF=2VPP at 1kHz
+ 2.048V DC, DAC code 0
VREF= 0.4VPP + 2.048V DC,
DAC code 2048
Slow
Fast
-84
1.9
2.2
dB
MHz
MHz
Low reference voltage
High reference voltage
Output source current
Output sink current
Load Capacitance
VREFOUTL
VREFOUTH
IREFSRC
IREFSNK
VDD > 4.75V
in parallel with 100nF cap.
1.010
2.020
1.024
2.048
-1
1 10
1.040
2.096
1
V
V
mA
mA
µF
PSRR
60 dB
Digital Inputs
High level input current
Low level input current
Input capacitance
IIH Input voltage = DVDD
1 µA
IIL
Input voltage = 0V
-1
µA
CI 8 pF
Notes:
1. Integral non-linearity (INL) is the maximum deviation of the output from the line between zero and full scale excluding the
effects of zero code and full scale errors).
2. Differential non-linearity (DNL) is the difference between the measured and ideal 1LSB amplitude change
of any adjacent two codes. A guarantee of monotonicity means the output voltage changes in the same
direction (or remains constant) as a change in digital input code.
3. Zero code error is the voltage output when the DAC input code is zero.
4. Gain error is the deviation from the ideal full-scale output excluding the effects of zero code error.
5. Power supply rejection ratio is measured by varying AVDD from 4.5V to 5.5V and measuring the
proportion of this signal imposed on the zero code error and the gain error.
6. Zero code error and Gain error temperature coefficients are normalised to full-scale voltage.
7. Output load regulation is the difference between the output voltage at full scale with a 10kΩ load and 2kΩ
load. It is expressed as a percentage of the full scale output voltage with a 10kΩ load.
8. IDD is measured while continuously writing code 2048 to the DAC. For VIH < DVDD - 0.7V and VIL > 0.7V
supply current will increase.
9. Slew rate results are for the lower value of the rising and falling edge slew rates.
10. Settling time is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising and falling
edges. Limits are ensured by design and characterisation, but are not production tested.
WOLFSON MICROELECTRONICS LTD
PD Rev 1.1 February 2001
5
5 Page 
Production Data
WM2630
DAC A TO H CODE REGISTERS
Addresses 0 to 7 are the DAC registers. The data written to these registers is transferred to the
respective DAC when the LOADB input (pin 18) is low. For instantaneous updating, LOADB can be held
low permanently.
CONTROL REGISTER 0
Control register 0 (address 8) is used to select functions that apply to the whole IC, such as Power Down
and Data Input Format.
BIT D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Function
X X X X X X X PD DO R1 R0 IM
Default
X X XXXXX 0 0 0 0 0
Table 5 Register Map
BIT DESCRIPTION
PD Full device Power Down
DO DOUT Enable
R1 Int / Ext Reference Select
R0 Internal Reference Select
IM Input Mode
X Reserved
Table 6 Register Map
0
Normal
Disabled
External
1.024V
Straight Binary
1
Power Down
Enabled
Internal
2.048V
Two’s Complement
CONTROL REGISTER 1
Control register 1 (address 9) is used to power down individual pairs of DACs and select their settling
time. Powering down a pair of DACs disables their amplifiers and reduces the power consumption of the
device. The settling time in fast mode is typically 1µs. In slow mode, the settling time is typically 3µs and
power consumption is reduced.
BIT D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Function
Default
X X X X PGH PEF PCD PAB SGH SEF SCD SAB
X X XX0 0 0 0 0 0 0 0
Table 7 Register Map
BIT DESCRIPTION
PXY Power Down DACs X and Y
SXY Speed Setting for DACs X and Y
Table 8 Register Map
0
Normal
Slow
1
Power Down
Fast
DAC PRESET REGISTER
The Preset register (address 10) makes it possible to update all eight DACs at the same time. The value
stored in this register becomes the digital input to all the DACs when the asynchronous PREB input (pin
5) is driven low. If no data has previously been written to the preset register, all DACs are set to zero
scale.
TWO-CHANNEL REGISTERS
The two-channel registers (addresses 12 to 15) provide a ‘differential output’ function where writing data
to one DAC will automatically write the complement to the other DAC in the pair. For example, writing a
hexadecimal value of FFFF to address 12 will set DAC A to full scale and DAC B to zero scale.
WOLFSON MICROELECTRONICS LTD
PD Rev 1.1 February 2001
11
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet WM2630.PDF ] | |
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