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PDF WM5628 Data sheet ( Hoja de datos )

Número de pieza WM5628
Descripción 3 & 5V Octal 8-Bit Voltage Output DAC with Serial Interface
Fabricantes Wolfson Microelectronics plc 
Logotipo Wolfson Microelectronics plc Logotipo



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No Preview Available ! WM5628 Hoja de datos, Descripción, Manual

WM5628L, WM5628
Production Data
Sept. 1996 Rev 2
3 & 5V Octal 8-Bit Voltage Output DAC
with Serial Interface
Description
WM5628L and WM5628 are Octal 8-bit digital to analogue
converters (DAC) controlled via a serial interface. Each
DAC's output voltage range is programmable for either x1
or x 2 its reference input voltage, allowing near rail to rail
operation for the x 2 output range. High impedance
buffered voltage reference inputs are provided for each
group of four DACs. WM5628L operates on a single
supply voltage of 3 V while WM5628 operates on 5 V.
WM5628/L interfaces to all popular microcontrollers and
microprocessors via a three wire serial interface with CMOS
compatible, schmitt trigger, digital inputs. An 12 bit
command word comprises 3 DAC select bits, an output
range selection bit and 8-bits of data.
Individual or all DAC outputs are changed using
WM5628/L's double buffered DAC registers and the
separate LOAD and LDAC inputs. DAC outputs are
updated simultaneously by writing a complete set of new
values and then pulsing the LDAC input.
The DAC outputs are optimised for single supply
operation and driving ground referenced loads.
An internal power-on-reset function sets the DAC's input
codes to zero at power up.
Ideal in space critical applications WM5628/L is available
in wide-bodied and DIP packages for commercial (0oC to
70oC) and industrial (-40oC to 85oC) temperature ranges.
Pin Configuration
Features
• Eight 8-bit voltage output DAC's
• Three wire serial interface
• Programmable x1 or x 2 output range.
• Power-on-reset sets outputs to zero
• Buffered voltage reference inputs
• Simultaneous DAC output update
Key Specifications
• Single supply operation:
WM5628L : 3 V
WM5628 : 5 V
• 0 to 4 V output (x 2 output range) at 5 V VDD
• 0 to 2.5 V output (x 2 output range) at 3 V VDD
• Guaranteed monotonic output
Applications
• Programmable d.c. voltage sources
• Digitally controlled attenuator/amplifier
• Signal synthesis
• Mobile communications
• Automatic test equipment
• Process control
Ordering Information
Top View
16 pin N and DW packages
DACB
DACA
GND
Data
CLK
VDD
DACE
DACF
1
2
3
4
5
6
7
8
16 DACC
15 DACD
14 Ref1
13 LDAC
12 Load
11 Ref2
10 DACH
9 DAC G
DEVICE
TEMP. RANGE
WM5628CN
0oC to 70oC
WM5628CDW
WM5628IN
WM5628IDW
WM5628LCN
WM5628LCDW
WM5628LIN
WM5628LIDW
0oC to 70oC
-40oC to 85oC
-40oC to 85oC
0oC to 70oC
0oC to 70oC
-40oC to 85oC
-40oC to 85oC
PACKAGE
16 pin plastic DIP
16 pin wide-bodied plastic SO
16 pin plastic DIP
16 pin wide-bodied plastic SO
16 pin plastic DIP
16 pin wide-bodied plastic SO
16 pin plastic DIP
16 pin wide-bodied plastic SO
Production Data data sheets contain
final specifications current on publication
date. Supply of products conforms to
Wolfson Microelectronics standard terms
and conditions
Wolfson Microelectronics © 1996 Wolfson Microelectronics
Lutton Court, Bernard Terrace, Edinburgh EH8 9NX, UK
Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176
www: http://www.wolfson.co.uk

1 page




WM5628 pdf
WM5628L, WM5628
Electrical Characteristics: WM5628 & WM5628L (continued)
VDD = 3 .6V, GND = 0 V, VREF = 2 V x 1 gain, RL = 10 k, CL = 100 pF, TA = full range, unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
Dynamic Performance
Output settling time
To 1/2LSB, VDD=3V & 5V (note 13)
Output slew rate
Input bandwidth
(note 14)
Large Signal Bandwidth
Measured at -3dB point
Digital Crosstalk
Clk = 1MHz sq wave measured at
DACA - DACD
MIN
TYP
10
1
100
100
-50
MAX UNIT
µs
V/µs
kHz
kHz
dB
Notes:
1. Absolute Maximum Ratings are stress ratings only.
Permanent damage to the device may be caused by
continuously operating at or beyond these limits.
Device functional operating range limits are given
under Recommended Operating Conditions.
Guaranteed performance specifications are given
under Electrical Characteristics at the test conditions
specified.
2. Total Unadjusted Error is the sum of integral linearity
error, zero code error and full scale error over the input
code range.
3. Differential Nonlinearity (DNL) is the difference
between the measured and ideal 1 LSB amplitude
change of any two adjacent codes. A guarantee of
monotonicity means the output voltage changes in the
same direction (or remains constant) as a change in
the digital input code.
4. Integral Nonlinearity (INL) is the maximum deviation of
the output from the line between zero and full scale
(excluding the effects of zero code and full-scale
errors).
5. Zero code error is the deviation from zero voltage
output when the digital input code is zero.
6. Zero code error temperature coefficient is given by:
6
ZCETC = (ZCE(Tmax - ZCE(Tmin)) /VREF x 10 / (Tmax
- Tmin)
7. Zero-code Error Rejection Ratio (ZCE-RR) is
measured by varying the VDD voltage, from 4.5 to 5.5
V d.c., and measuring the proportion of this signal
imposed on the zero-code output voltage.
8. Full-scale error is the deviation from the ideal full-scale
output (VREF - 1LSB) with an output load of 10k
9. Full-Scale Temperature Co-efficient is given by:
FSETC = (FSE(Tmax) - FSE(Tmin)) / VREF x 106
/ Tmax - T min)
10. Full Scale Error Rejection Ratio (FSE-RR) is
measured by varying the VDD voltage from 4.5 to
5.5 V d.c. and measuring the proportion of this signal
imposed on the full-scale output voltage
11 Reference feedthrough is measured at a DAC output
with an input code = 00 Hex with a VREF input = 1 Vdc
+ 1 VPP at 10kHz
12. Channel to channel isolation is measured at a DAC
output with an input code of one DAC to FF Hex and
the code oa all other DACs to oo Hex with a VREF in-
put = 1 Vdc + 1 Vpp at 10kHz
13 Setting time is the time for the output signal to remain
within ±0.5 LSB of the final measurement value for a
digital input code change of 00 Hex to FF Hex. For
WM 5628: VDD = 5V, VREF = 2V and range = x 2. For
WM5628L: VDD = 3, VREF = 1.25V and range = x 2.
14 Reference bandwidth is the -3dB bandwidth with an
input at VREF = 1.25 Vdc =+ 2 Vpp with a digital input
code of full-scale.
Wolfson Microelectronics
5

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WM5628 arduino
Pin Descriptions
Pin Name
1 DACB
2 DACA
3 GND
4 Data
5 CLK
6 VDD
7 DACE
8 DACF
9 DACG
10 DACH
11 Ref2
12 Load
13 LDAC
14 Ref1
15 DACD
16 DACC
Type
Analogue output
Analogue input
Supply
Digital input
Digital input
Supply
Analogue output
Analogue output
Analogue output
Analogue output
Analogue input
Digital input
Digital input
Analogue input
Analogue output
Analogue output
WM5628L, WM5628
Function
DAC B output
DAC A output
Ground return
Serial data input
Serial interface clock, negative edge sensitive
Positive supply voltage
DAC E output
DAC F output
DAC G output
DAC H output
Reference to DACE, DACF, DACG and DACH
Serial input load
DAC update latch control
Reference to DACA, DACB, DACC and DACD
DAC D output
DAC C output
Functional Description
DAC operation
Each of WM5628/L 's eight digital to analogue converters
(DACs) are implemented using a single resistor string with
256 taps corresponding to each of the input 8-bit codes.
One end of a resistor string is connected to the GND pin
and the other end is driven from the output of a reference
input buffer. The use of a resistor string guarantees
monotonicity of the DAC's output voltage. Linearity depends
upon the matching of the resistor string's individual elements
and the performance of the output buffer. Two high input
impedance voltage reference buffers are provided, each
driving four DACs,
Each DAC has a voltage output amplifier which is
programmable for gains of x1 or x 2 through the serial
interface. The DAC output amplifiers feature rail to rail
output stages, allowing outputs over the full supply voltage
range to be achieved with a x 2 gain setting and a VDD/2
reference voltage input. Used in this way a slight
degradation in linearity will occur as the output voltage
approaches VDD.
A power-on-reset activates at power up resetting the DACs
inputs to code 0. Each output voltage is given by:
Vout = Vref x CODE/256 x (RNG+1 )
Where: RNG controls the output gains of x 1 and x 2
CODE is the range 0 to 255
Data Interface
WM5628/L's eight double buffered DAC inputs allow
several ways of controlling the update of each DAC's
output.
Serial data is input, MSB first, into the DATA input pin Serial
Input DAC Address and Output Tables using CLK, LOAD
and LDAC control inputs and comprises 3 DAC address
bits, an output range (RNG) bit and 8 DAC input bits.
With the LOAD pin high data is clocked into the DATA pin
on each falling edge of CLK. Any number of data bits may
be clocked in, only the last 12 bits are used. When all data
bits have been clocked in, a falling edge at the LOAD pin
latches the data and RNG bits into the correct 9 bit input
latch using the 3 bit DAC address.
If the LDAC input pin is low, the second latch at the DAC
input is transparent, and the DAC input and RNG bit will be
updated on the falling edge of LOAD simultaneously with
the input latch, as shown in figure 1. If the LDAC input is high
during serial data input, as shown in figure 2, the falling edge
of the LOAD input stores the data in the addressed input
latch. The falling edge of LDAC updates the second latches
from the input latches and hence the DAC outputs.
Wolfson Microelectronics
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