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PDF WM8720 Data sheet ( Hoja de datos )
| Número de pieza | WM8720 | |
| Descripción | 24-bit/ 96kHz Stereo DACwith Volume Control | |
| Fabricantes | Wolfson Microelectronics plc | |
| Logotipo |  |
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WM8720
24-bit, 96kHz Stereo DAC with Volume Control
Production Data, November 2000, Rev 3.0
DESCRIPTION
The WM8720 is a high performance stereo DAC designed
for audio applications such as CD, DVD, home theatre
systems, set top boxes and digital TV. The WM8720
supports data input word lengths from 16 to 24-bits and
sampling rates up to 96kHz. The WM8720 consists of a
serial interface port, digital interpolation filter, multi-bit
sigma delta modulator and stereo DAC in a small 20-pin
SSOP package. The WM8720 also includes a digitally
controllable mute and attenuator function on each channel.
The WM8720 supports a variety of connection schemes for
audio DAC control. The SPI-compatible serial control port
provides access to a wide range of features including on-
chip mute, attenuation and phase reversal. A hardware
controllable interface is also available.
The programmable data input port supports a variety of
glueless interfaces to popular DSPs, audio decoders and
S/PDIF and AES/EBU receivers.
FEATURES
• Performance:
- 102dB SNR (‘A’ weighted @48kHz),
- THD: -95dB @ 0dB FS
• 5V or 3.3V supply operation
• Sampling frequency: 8kHz to 96kHz
• Input data word: 16 to 24-bit
• Hardware or SPI compatible serial port control modes:
- Hardware mode: system clock, reset, mute,
de-emphasis
- Serial control mode: mute, de-emphasis, digital
attenuation (256 steps), zero mute, phase reversal,
power down
• Compatible with PCM1720
APPLICATIONS
• CD, DVD audio
• Home theatre systems
• Set top boxes
• Digital TV
BLOCK DIAGRAM
SCKI
(2)
ML/I2S MC/IWL MD/DM PWDN RSTB MODE MUTE
(4) (5) (6)
(1) (7) (18) (17)
BCKIN (14)
LRCIN (16)
DIN (15)
256fs/384fs
SERIAL
INTERFACE
DIGITAL
FILTERS
CONTROL INTERFACE
MUTE/
ATTEN
SIGMA
DELTA
MODULATOR
WM8720
(3) TEST
(8) ZERO
DAC
(9) VOUTR
MUTE/
ATTEN
SIGMA
DELTA
MODULATOR
DAC
(12) VOUTL
(20) (10) (13) (11) (19)
DGND AGND CAP AVDD DVDD
WOLFSON MICROELECTRONICS LTD
Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK
Tel: +44 (0) 131 667 9386
Fax: +44 (0) 131 667 5176
Email: [email protected]
http://www.wolfson.co.uk
Production Data Datasheets contain final
specifications current on publication date.
Supply of products conforms to Wolfson
Microelectronics’ Terms and Conditions.
2000 Wolfson Microelectronics Ltd.
1 page  
Production Data
WM8720
LRCIN
BCKIN
DIN
tBCH
tBCL
tBCY
tDS
tBL
tDH
tLB
Figure 1 Audio Data Input Timing
Test Conditions
AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated.
PARAMETER
SYMBOL
Audio Data Input Timing Information
BCKIN pulse cycle time
BCKIN pulse width high
BCKIN pulse width low
BCKIN rising edge to
LRCIN edge
tBCY
tBCH
tBCL
tBL
LRCIN rising edge to
BCKIN rising edge
tLB
DIN setup time
tDS
DIN hold time
tDH
TEST CONDITIONS
MIN TYP
100
40
40
20
20
20
20
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
SCKI
tSCKIL
tSCKIH
tSCKY
Figure 2 System Clock Timing Requirements
Test Conditions
AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated.
PARAMETER
SYMBOL
System Clock Timing Information
System clock pulse width high
System clock pulse width low
System clock cycle time
tSCKIH
tSCKIL
tSCKY
TEST CONDITIONS
MIN TYP
10
10
27
MAX
UNIT
ns
ns
ns
WOLFSON MICROELECTRONICS LTD
PD Rev 3.0 November 2000
5
5 Page 
Production Data
WM8720
SOFTWARE CONTROL INTERFACE
The WM8720 can be controlled using a 3-wire serial interface. MD/DM (pin 6) is used for the program
data, MC/IWL (pin 5) is used to clock in the program data and ML/I2S (pin 4) is use to latch in the
program data. The 3-wire interface protocol is shown in Figure 7.
ML/I2S
MC/IWL
MD/DM
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Figure 7 3-Wire Serial Interface
REGISTER MAP
WM8720 controls the special functions using 4 program registers, which are 16-bits long. These
registers are all loaded through input pin MD/DM. After the 16 data bits are clocked in, ML/I2S/IWL is
used to latch in the data to the appropriate register. Table 7 shows the complete mapping of the
4 registers.
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
M0 -- - - - - A1 A0 LDL AL7 AL6 AL5 AL4 AL3 AL2 AL1 AL0
M1 - - - - - A1 A0 LDR AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0
M2 - - - - - A1 A0 PL3 PL2 PL1 PL0 IW1 IW0 OPE DE MU
M3 - - - - - A1 A0 IZD SF1 SF0 - - - ATC LRP I2S
Table 7 Mapping of Program Registers
REGISTER NAME
Register 0 (M0)
A[1:0] = 00
Register 1 (M1)
A[1:0] = 01
Register 2 (M2)
A[1:0] = 10
Register 3 (M3)
A[1:0] = 11
BIT NAME
AL[7:0]
LDL
AR[7:0]
LDR
MU
DE
OPE
IW[1:0]
PL[3:0]
I2S
LRP
ATC
SF[1:0]
IZD
Table 8 Internal Register Mapping
DEFAULT
1111 1111
0
1111 1111
0
0
0
0
00
1001
0
0
0
00
0
DESCRIPTION
DAC attenuation data for left channel
Attenuation data load control for left channel
DAC attenuation data for right channel
Attenuation data load control for right channel
Left and right DACs soft mute control
De-emphasis control
Left and right DACs operation control
Input audio word resolution
DAC output control
Audio data format select
Polarity of LRCIN (pin 7) select
Attenuator control
Sampling rate select
Infinite zero detection circuit control and automute control
DAC OUTPUT ATTENUATION
Register 0 (A[1:0] = 00) is used to control left channel attenuation. Bits 0-7 (AL[7:0]) are used to
determine the attenuation level Table 9. The level of attenuation is given by:
Attenuation = [20.log10 (Attenuation_Data/256)] dB ...................................................................................................Eqn. 1
WOLFSON MICROELECTRONICS LTD
PD Rev 3.0 November 2000
11
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