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PDF WM9710 Data sheet ( Hoja de datos )
| Número de pieza | WM9710 | |
| Descripción | AC97 Audio CODEC and Mixer with Integrated Headphone Driver | |
| Fabricantes | Wolfson Microelectronics plc | |
| Logotipo |  |
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WM9710
AC’97 Audio CODEC and Mixer with
Integrated Headphone Driver
DESCRIPTION
FEATURES
The WM9710 is a high-quality stereo audio codec with an
integrated headphone driver.
The device is compliant with the Intel AC’97 Rev 2.2
specification. It performs full-duplex 18-bit codec functions and
supports variable sample rates from 8kHz to 48kHz with high
signal to noise ratio. Analogue mixers are included to mix
external analogue signals into the playback or record path.
The WM9710 allows designers to easily integrate phone
functions with other audio functions such as MP3 playback and
voice recording. Mono inputs and outputs are provided to
connect to an external voice codec. The on-chip headphone
driver can distinguish between a stereo headphone and mono
headset, and route the signals accordingly.
Optional AC’97 features include 3D sound enhancement,
primary/secondary mode operation and S/PDIF or I2S output.
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AC’97 rev2.2 compliant, 18-bit stereo codec
Integrated headphone driver
Automatic headset detection and switching (for stereo
headphones / mono phone headsets)
Separately mixed mono output for phone TX path (also
includes headphone buffer for mono earpiece)
Multiple channel input mixer
Mono inputs for phone RX and PCBEEP signals
On-chip sample rate conversion, supports rates from 8kHz
to 48kHz. DAC and ADC rates are fully independent.
Optional S/PDIF or I2S digital audio output
3V to 5V operation
Each circuit block can be separately powered on or off
Leadless 7mm × 7mm × 0.9mm QFN or 48-pin TQFP
package
The 5-pin bi-directional AC-Link interface transfers control data,
DAC and ADC words to and from the AC’97 controller. The
WM9710 is fully operable on 3V or 5V or mixed 3/5V supplies,
and is packaged in a leadless, chip scale QFN package with
7mm body size or 48-pin TQFP package.
APPLICATIONS
• Personal Digital Assistants and ‘Smartphones’
• WinCE systems
BLOCK DIAGRAM
DGND1 DVDD1
DGND2 DVDD2
CX3D1 CX3D2
W
WM9710
LINEINL
LINEINR
CDL
CDGND
CDR
MIC2
MIC1
VREFOUT
MIC SELECT
(Reg 20h) M
U
MX
MIC BOOST
(Reg 0Eh)
0/20
dB
U
X headset autodetect
HPOUTL
PHONE
VREF
LINEINVOL (Reg 10h)
MICVOL (Reg 0Eh)
CDVOL (Reg 12h)
RECORD
GAIN
(Reg 1Ch)
M
U
X
RECORD
SELECT
(Reg 1Ah)
ADC
L
ADC
R
DIGITAL
FILTERS
Σ∆
MODULATION
VARIABLE
RATE AUDIO
DAC
L
DAC
R
POP
(Reg 20h)
DACVOL
(Reg 18h)
(Reg 0Ah)
CONTROL LOGIC
AC'97
INTERFACE
CLOCK
OSC
3D
MIXVOL
(Reg 72h)
ADCNDAC MUX
(Reg 5Ch)
HPND
(Reg 5Ch) HPVOL
(Reg 04h)
M
U
X
16 / 32Ohm
headphone
HPOUTL
HPOUTR
HPGND
MASTER VOL
(Reg 02h)
LINEOUTL
LINEOUTR
PHIZ
(Reg 78h)
(Reg 0Ch)
M
U
X PSEL
(Reg 5Ch)
MIX
(Reg 20h)
M
U
X
MONO VOL
(Reg 06h)
MONO_OUT
(TX)
24.576MHz
WOLFSON MICROELECTRONICS plc
www.wolfsonmicro.com
Production Data, December 2003, Rev 4.0
Copyright 2003 Wolfson Microelectronics plc
1 page  
WM9710
PIN CONFIGURATION
Production Data
48 47 46 45 44 43 42 41 40 39 38 37
DVDD1 1
XTLIN 2
XTLOUT 3
DGND1 4
SDATAOUT 5
BITCLK 6
DGND2 7
SDATAIN 8
DVDD2 9
SYNC 10
RESETB 11
PCBEEP 12
WM9710
QFN
36 LINEOUTR
35 LINEOUTL
34 CX3D2
33 CX3D1
32 CAP2
31 DNC
30 DNC
29 DNC
28 VREFOUT
27 VREF
26 DNC
25 DNC
13 14 15 16 17 18 19 20 21 22 23 24
Figure 1 QFN Pinout
DVDD1
XTLIN
XTLOUT
DGND1
SDATAOUT
BITCLK
DGND2
SDATAIN
DVDD2
SYNC
RESETB
PCBEEP
48 47 46 45 44 43 42 41 40 39 38 37
1 36
2 35
3 34
4 33
5 32
6 WWMM99771010 31
QFN7 TQFP 30
8 29
9 28
10 27
11 26
12 25
13 14 15 16 17 18 19 20 21 22 23 24
LINEOUTR
LINEOUTL
CX3D2
CX3D1
CAP2
DNC
DNC
DNC
VREFOUT
VREF
DNC
DNC
Figure 2 TQFP Pinout
w
PD Rev 4.0 December 2003
5
5 Page 
WM9710
DETAILED TIMING DIAGRAMS
Production Data
Test Characteristics:
AVDD = 3.3V, DVDD = 3.3V, AGND = 0V …………..TA = 0oC to +70oC, unless otherwise stated.
All measurements are taken at 10% to 90% DVDD, unless otherwise stated. All the following timing information is guaranteed,
not tested.
AC-LINK LOW POWER MODE
SLOT 1 SLOT 2
SYNC
BITCLK
SDATAOUT
WRITE
TO 0X20
DATA PR4
tS2_PDOWN
SDATAIN
DON'T
CARE
COLD RESET
Figure 4 AC-Link Powerdown Timing
PARAMETER
End of slot 2 to BITCLK SDATAIN
low
SYMBOL
tS2_PDOWN
MIN
TYP
MAX
1.0
UNIT
µs
RESETB
tRST_LOW
tRST2CLK
BITCLK
Figure 5 Cold Reset Timing
Note:
For correct operation SDATAOUT and SYNC must be held LOW for entire RESETB active low
period otherwise the device may enter test mode. See AC’97 specification or Wolfson
applications note WAN104 for more details.
PARAMETER
RESETB active low pulse width
RESETB inactive to BITCLK
startup delay
SYMBOL
tRST_LOW
tRST2CLK
MIN
1.0
162.8
TYP
MAX
UNIT
µs
ns
w
PD Rev 4.0 December 2003
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet WM9710.PDF ] | |
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