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WS27C256L-12CMB PDF даташит

Спецификация WS27C256L-12CMB изготовлена ​​​​«STMicroelectronics» и имеет функцию, называемую «Military 32K x 8 CMOS EPROM».

Детали детали

Номер произв WS27C256L-12CMB
Описание Military 32K x 8 CMOS EPROM
Производители STMicroelectronics
логотип STMicroelectronics логотип 

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WS27C256L-12CMB Даташит, Описание, Даташиты
WS27C256L
Military 32K x 8 CMOS EPROM
KEY FEATURES
High Performance CMOS
— 120 ns Access Time
Fast Programming
DESC SMD No. 5962-86063
Ceramic Leadless Chip Carrier (CLLCC)
EPI Processing
— Latch-Up Immunity to 200 mA
— ESD Protection Exceeds 2000 Volts
300 Mil DIP or Standard 600 Mil DIP
JEDEC Standard Pin Configuration
GENERAL DESCRIPTION
The WS27C256L is a performance oriented 256K UV Erasable Electrically Programmable Read Only Memory
organized as 32K words x 8 bits/word. It is manufactured using an advanced CMOS technology which enables it to
operate at speeds up to 120 nsecs. The memory was designed utilizing WSI's patented self-aligned split gate
EPROM cell, resulting in a low power device with a very cost effective die size.
The WS27C256L 256K EPROM provides 32K of 8 bit wide code store capacity for DSP, microprocessor, and
microcontroller-based systems. Its 120 nsec access time over the full Military temperature range provides the
potential of no-wait state operation. And where this parameter is important, the WS27C256L provides the user with
a very fast 35 nsec TOE output enable time.
The WS27C256L is offered in a 28 pin 300 mil skinny CERDIP or the standard 600 mil CERDIP, and also in a
32 pad Ceramic Leadless Chip Carrier (CLLCC) for surface mount applications. All packages incorporate the
standard JEDEC EPROM pinout.
PIN CONFIGURATION
Chip Carrier
TOP VIEW
CERDIP
A6
4
5
3
2
1
32 31 30
29
A8
A5 6
28 A9
A4 7
27 A11
A3 8
26 NC
A2 9
25 OE
A1 10
24 A10
A0 11
23 CE/PGM
NC 12
22 O7
O0 13
21 O6
14 15 16 17 18 19 20
O1 O2 NC O3 O4 O5
PRODUCT SELECTION GUIDE
PARAMETER
Address Access Time (Max)
Chip Select Time (Max)
Output Enable Time (Max)
Return to Main Menu
WS27C256L-12
120 ns
120 ns
35 ns
VPP
A12
A7
A6
A5
A4
A3
A2
A1
A0
O0
O1
O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 VCC
27 A14
26 A13
25 A8
24 A9
23 A11
22 OE
21 A10
20 CE/PGM
19 O7
18 O6
17 O5
16 O4
15 O3
WS27C256L-15
150 ns
150 ns
40 ns
WS27C256L-20
200 ns
200 ns
40 ns
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WS27C256L-12CMB Даташит, Описание, Даташиты
WS27C256L
ABSOLUTE MAXIMUM RATINGS*
Storage Temperature............................–65° to + 150°C
Voltage on any Pin with
Respect to Ground ....................................–0.6V to +7V
VPP with Respect to Ground...................–0.6V to + 14V
VCC Supply Voltage with
Respect to Ground ....................................–0.6V to +7V
ESD Protection ..................................................>2000V
OPERATING RANGE
RANGE
TEMPERATURE
Military
–55°C to +125°C
VCC
+5V ± 10%
*NOTICE:
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of
the device at these or any other conditions above
those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of
time may affect device reliability.
DC READ CHARACTERISTICS Over Operating Range. (See Above)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN MAX
VIL Input Low Voltage
VIH Input High Voltage
VOL Output Low Voltage
VOH Output High Voltage
IOL = 2.1 mA
IOH = –400 µA
–0.5
2.0
3.5
0.8
VCC + 1
0.4
ISB1 VCC Standby Current (CMOS) CE = VCC ± 0.3 V (Note 2)
ISB2 VCC Standby Current
CE = VIH
ICC VCC Active Current
CE = OE = VIL
(Note 1)
F = 5 MHz
F = 8 MHz
100
1
40
50
IPP VPP Supply Current
VPP VPP Read Voltage
ILI Input Leakage Current
VPP = VCC
VIN = 5.5 V or Gnd
VCC –0.4
–10
100
VCC
10
ILO Output Leakage Current
VOUT = 5.5 V or Gnd
–10 10
NOTES: 1. The supply current is the sum of ICC and IPP. The maximum current value is with Outputs O0 to O7 unloaded.
2. CMOS inputs: VIL = GND ± 0.3V, VIH = VCC ± 0.3 V.
UNITS
V
V
V
V
µA
mA
mA
mA
µA
V
µA
µA
AC READ CHARACTERISTICS Over Operating Range (See Above)
SYMBOL
PARAMETER
WS27C256L-12 WS27C256L-15 WS27C256L-20
UNITS
MIN MAX MIN MAX MIN MAX
t ACC
t CE
tOE
t DF
Address to Output Delay
CE to Output Delay
OE to Output Delay
Output Disable to Output Float
(Note 3)
120 150 200
120 150 200
35 40 40
ns
35 40 40
Output Hold From Addresses,
tOH CE or OE, Whichever Occurred
0
0
0
First (Note 3)
NOTE: 3. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer driven – see timing
diagram.
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WS27C256L-12CMB Даташит, Описание, Даташиты
AC READ TIMING DIAGRAM
WS27C256L
ADDRESSES
VIH
VIL
VIH
CE
VIL
VIH
OE
VIL
OUTPUT
VIH
VIL
ADDRESS VALID
tCE(4)
tACC
HIGH Z
tOE(4)
tOH
tDF(5)
VALID OUTPUT
HIGH Z
NOTE: 4. OE may be delayed up to tCE – tOE after the falling edge of CE without impact on tCE.
CAPACITANCE(5) TA = 25°C, f = 1 MHz
SYMBOL
PARAMETER
CONDITIONS
CIN
COUT
CVPP
Input Capacitance
Output Capacitance
VPP Capacitance
VIN = 0V
VOUT = 0V
VPP = 0 V
NOTES: 5. This parameter is only sampled and is not 100% tested.
6. Typical values are for TA = 25°C and nominal supply voltages.
TYP (6)
4
8
18
MAX
6
12
25
UNITS
pF
pF
pF
TEST LOAD (High Impedance Test Systems)
A.C. TESTING INPUT/OUTPUT WAVEFORM
2.01 V
D.U.T.
820
100 pF
(INCLUDING SCOPE
AND JIG
CAPACITANCE)
2.4
0.4
2.0
TEST
POINTS
0.8
2.0
0.8
A.C. testing inputs are driven at 2.4 V for a logic "1" and 0.4 V
for a logic "0." Timing measurements are made at 2.0 V for a
logic "1" and 0.8 V for a logic "0".
NOTE: 7. Provide adequate decoupling capacitance as close as possible to this device to achieve the published A.C. and D.C. parameters.
A 0.1 microfarad capacitor in parallel with a 0.01 microfarad capacitor connected between VCC and ground is recommended.
Inadequate decoupling may result in access time degradation or other transient performance failures.
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STMicroelectronics

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