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WS57C256F-55J PDF даташит

Спецификация WS57C256F-55J изготовлена ​​​​«STMicroelectronics» и имеет функцию, называемую «HIGH SPEED 32K x 8 CMOS EPROM».

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Номер произв WS57C256F-55J
Описание HIGH SPEED 32K x 8 CMOS EPROM
Производители STMicroelectronics
логотип STMicroelectronics логотип 

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WS57C256F-55J Даташит, Описание, Даташиты
WS57C256F
HIGH SPEED 32K x 8 CMOS EPROM
Fast Access Time
KEY FEATURES
Immune to Latch-UP
— tACC = 35 ns
— tCE = 35 ns
Low Power Consumption
— 200 µA Standby ICC
— Up to 200 mA
ESD Protection Exceeds 2000 Volts
Available in 300 Mil DIP and PLDCC
DESC SMD No. 5962-86063
GENERAL DESCRIPTION
The WS57C256F is a High Performance 32K x 8 UV Erasable EPROM. It is manufactured using an advanced
CMOS process technology enabling it to operate at speeds as fast as 35 ns Address Access Time (tACC) and 35 ns
Chip Enable Time (tCE). It was designed utilizing WSI's patented self-aligned split gate EPROM cell, resulting in a
low power device with a very cost effective die size. The low standby power capability of this 256 K product (200 µA
in a CMOS interface environment) is especially attractive.
This product, with its high speed capability, is particularly appropriate for use with today's fast DSP processors and
high-clock-rate Microprocessors. The WS57C256F's 35 ns speed enables these advanced processors to operate
without introducing any undesirable wait states. The WS57C256F is also ideal for use in modem applications, and is
recommended for use in these applications by the leading modem chip set manufacturer.
The WS57C256F is available in a variety of package types including the space saving 300 Mil DIP, the surface
mount PLDCC, and other windowed and non-windowed options. And its standard JEDEC EPROM pinouts provide
for automatic upgrade density paths for current 64K and 128K EPROM users.
MODE SELECTION
PINS CE/
MODE
PGM
OE
A9
A0
VPP VCC OUTPUTS
Read
Output
Disable
VIL VIL X
X VIH X
X VCC VCC DOUT
X VCC VCC High Z
Standby
Program
Program
Verify
VIH X
VIL VIH
X
X
X VIL X
X VCC VCC
X VPP2 VCC
High Z
DIN
X VPP2 VCC DOUT
Program
Inhibit
Signature3
VIH VIH X X VPP2 VCC
VIL VIL VH2 VIL VCC VCC
VIL VIL VH2 VIH VCC VCC
High Z
23 H4
EO H5
NOTES:
1. X can be VIL or VIH.
2. VIH = VPP = 12.75 ± 0.25 V.
3. A1 – A8, A10 – A14 = VIL.
4. Manufacturer Signature.
5. Device Signature.
PRODUCT SELECTION GUIDE
PARAMETER
Address Access Time (Max)
Output Enable Time (Max)
WS57C256F-35
35 ns
15 ns
PIN CONFIGURATION
TOP VIEW
Chip Carrier
CERDIP
VPP 1
A6
4
5
3
2
1
32 31 30
29
A8
A12 2
A7 3
A5 6
28
A4 7
27
A3 8
26
A2 9
25
A1 10
24
A0 11
23
NC 12
22
O0 13
21
14 15 16 17 18 19 20
A9
A11
NC
OE
A10
CE/PGM
O7
O6
A6 4
A5 5
A4 6
A3 7
A2 8
A1 9
A0 10
O0 11
O1 12
O2 13
O1 O2 NC O3 O4 O5
GND 14
28 VCC
27 A14
26 A13
25 A8
24 A9
23 A11
22 OE
21 A10
20 CE/PGM
19 O7
18 O6
17 O5
16 O4
15 O3
WS57C256F-45
45 ns
20 ns
WS57C256F-55
55 ns
25 ns
WS57C256F-70
70 ns
30 ns
Return to Main Menu
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WS57C256F-55J Даташит, Описание, Даташиты
WS57C256F
ABSOLUTE MAXIMUM RATINGS*
Storage Temperature............................–65° to + 150°C
Voltage on any Pin with
Respect to Ground ....................................–0.6V to +7V
VPP and A9 with Respect to Ground ......–0.6V to + 14V
ESD Protection ..................................................>2000V
OPERATING RANGE
RANGE
TEMPERATURE
Commercial
0°C to +70°C
Industrial
–40°C to +85°C
Military
–55°C to +125°C
VCC
+5V ± 10%
+5V ± 10%
+5V ± 10%
*NOTICE:
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of
the device at these or any other conditions above
those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of
time may affect device reliability.
DC READ CHARACTERISTICS Over Operating Range with VPP = VCC
SYMBOL
PARAMETER
TEST CONDITIONS
MIN MAX UNITS
VIL Input Low Voltage
VIH Input High Voltage
VOL Output Low Voltage
VOH Output High Voltage
(Note 4)
(Note 4)
IOL = 16 mA
IOH = – 4 mA
– 0.1
2.0
2.4
0.8
VCC + 0.3
0.4
V
V
V
V
ISB1
VCC Standby Current (CMOS)
CE = VCC ± 0.3 V
(Note 1)
Comm'l
Ind/Mil
200 µA
500 µA
ISB2 VCC Standby Current (TTL) CE = VIH (Note 2)
Comm'l
Ind/Mil
3 mA
5 mA
ICC1
VCC Active Current (CMOS)
(Notes 1 and 3)
Outputs Not Loaded
Comm'l
Ind/Mil
25 mA
30 mA
ICC2 VCC Active Current (TTL)
(Notes 2 and 3)
Outputs Not Loaded
Comm'l
Ind/Mil
50 mA
60 mA
IPP VPP Supply Current
VPP VPP Read Voltage
ILI Input Leakage Current
VPP = VCC
VIN = 5.5V or Gnd
VCC – 0.4
–10
100
VCC
10
µA
V
µA
ILO Output Leakage Current
VOUT = 5.5 V or Gnd
–10 10 µA
NOTES:
1. CMOS inputs: GND ± 0.3V or VCC ± 0.3V.
2. TTL inputs: VIL 0.8V, VIH 2.0V.
3. Add 3 mA/MHz for A.C. power component.
4. These are absolute voltages with respect to device ground pin and
include all overshoots due to system and/or tester noise.
Do not attempt to test these values without suitable equipment.
AC READ CHARACTERISTICS Over Operating Range. with VPP = VCC
PARAMETER
SYMBOL 57C256F-35 57C256F-45 57C256F-55 57C256F-70
MIN MAX MIN MAX MIN MAX MIN MAX
Address to Output Delay
CE to Output Delay
OE to Output Delay
Output Disable to Output Float
Address to Output Hold
tACC
tCE
tOE
tDF
tOH
35 45 55 70
35 45 55 70
15 20 25 30
20 20 25 30
0000
UNITS
ns
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WS57C256F-55J Даташит, Описание, Даташиты
AC READ TIMING DIAGRAM
ADDRESSES
CE
OE
OUTPUTS
VALID
tACC
tOH
tCE
tOE
tDF
VALID
tDF
WS57C256F
CAPACITANCE(5) TA = 25°C, f = 1 MHz
SYMBOL
PARAMETER
CONDITIONS
CIN
COUT
CVPP
Input Capacitance
Output Capacitance
VPP Capacitance
VIN = 0V
VOUT = 0V
VPP = 0 V
NOTES: 5. This parameter is only sampled and is not 100% tested.
6. Typical values are for TA = 25°C and nominal supply voltages.
TYP (6)
4
8
18
MAX
6
12
25
UNITS
pF
pF
pF
TEST LOAD (High Impedance Test Systems)
A.C. TESTING INPUT/OUTPUT WAVEFORM
2.01 V
D.U.T.
98
30 pF
(INCLUDING SCOPE
AND JIG
CAPACITANCE)
3.0 2.0
2.0
TEST
POINTS
0.0 0.8
0.8
A.C. testing inputs are driven at 3.0 V for a logic "1" and 0.0 V
for a logic "0." Timing measurements are made at 2.0 V for a
logic "1" and 0.8 V for a logic "0".
NOTE: 7. Provide adequate decoupling capacitance as close as possible to this device to achieve the published A.C. and D.C. parameters.
A 0.1 microfarad capacitor in parallel with a 0.01 microfarad capacitor connected between VCC and ground is recommended.
Inadequate decoupling may result in access time degradation or other transient performance failures.
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