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WS82C55A-5P PDF даташит

Спецификация WS82C55A-5P изготовлена ​​​​«Wing Shing Computer Components» и имеет функцию, называемую «CMOS Programmable peripheral Interface».

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Номер произв WS82C55A-5P
Описание CMOS Programmable peripheral Interface
Производители Wing Shing Computer Components
логотип Wing Shing Computer Components логотип 

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WS82C55A-5P Даташит, Описание, Даташиты
CMOS Programmable peripheral
Interface
WS82C55A
Features
Description
• Pin Compatible with NMOS 8255A
• 24 Programmable I/O Pins
• Fully TTL Compatible
• High Speed, No “Wait State” Operation with 5MHz
80C86 and 8MHz 80C88
• Direct Bit Set/Reset Capability
• Enhanced Control Word Read Capability
• L7 Process
• 2.5mA Drive Capability on All I/O Ports
• Low Standby Power (ICCSB) . . . . . . . . . . . . . . . . .10µA
Ordering Information
The WS82C55A is a high performance CMOS version of
the industry standard 8255A and is manufactured using a
self-aligned silicon gate CMOS process (Scaled SAJI IV). It
is a general purpose programmable I/O device which may be
used with many different microprocessors. There are 24 I/O
pins which may be individually programmed in 2 groups of
12 and used in 3 major modes of operation. The high
performance and industry standard configuration of the
WS82C55A make it compatible with the 80C86, and
other microprocessors.
Static CMOS circuit design insures low operating power. TTL
compatibility over the full military temperature range and bus
hold circuitry eliminate the need for pull-up resistors. The
advanced SAJI process results in performance equal
to or greater than existing functionally equivalent products at
a fraction of the power.
PART NUMBERS
WS82C55A-5P
WS82C55A-5C
WS82C55A-5Q
SPEED
5MHz
5MHz
5MHz
PART NUMBERS
WS82C55AP
WS82C55AC
WS82C55AQ
SPEED
8MHz
8MHz
8MHz
TEMPERATURE
RANGE
PKG.
oo
0 C to 70 C
40DIP
oo
0 C to 70 C
44 PLCC
oo
0 C to 70 C
44 QFP
Pinouts
PA3 1
40 PA4
PA2 2
39 PA5
PA1 3
38 PA6
PA0 4
37 PA7
RD 5
36 WR
CS 6
35 RESET
GND 7 WS82C55A-5P 34 D0
A1 8 WS82C55AP 33 D1
A0 9
32 D2
PC7 10
31 D3
PC6 11
30 D4
PC5 12
29 D5
PC4 13 DIP-40
PC0 14
28 D6
27 D7
PC1 15
PC2 16
26 VCC
25 PB7
PC3 17
24 PB6
PB0 18
23 PB5
PB1 19
22 PB4
PB2 20
21 PB3
CS
GND
A1
A0
PC7
PC6
PC5
PC4
PC0
PC1
PC2
1
2
3
4
5
6
7
8
9
10
11
WS82C55A-5Q
WS82C55AQ
QFP-44
33 RESET
32 D0
31 D1
30 D2.
29 D3
28 D4
27 D5
26 D6
25 D7
24 VCC
23 PB7
CS
GND
A1
A0
PC7
NC
PC6
PC5
PC4
PC0
PC1
6 5 4 3 2 1 44 43 42 41 40
7 39
8 38
9
WS82C55A-5C
37
10 WS82C55AC 36
11 35
12 34
13 33
14
PLCC-44
32
15 31
16 30
17 29
18 1920 21 22 23 24 25 26 27 28
RESET
D0
D1
D2
D3
NC
D4
D5
D6
D7
VCC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Wing Shing Computer Components Co., (H.K.)Ltd.
Homepage: http://www.wingshing.com
1
Tel:(852)2341 9276 Fax:(852)2797 8153









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WS82C55A-5P Даташит, Описание, Даташиты
Pin Description ( For DIP-40)
SYMBOL
VCC
PIN
NUMBER
26
TYPE
GND
D0-D7
7
27-34
I/O
RESET
35
I
CS 6
I
RD 5
I
WR 36
I
A0-A1
8, 9
I
PA0-PA7
1-4, 37-40
PB0-PB7
PC0-PC7
18-25
10-17
Functional Diagram
I/O
I/O
I/O
WS82C55A
DESCRIPTION
VCC: The +5V power supply pin. A 0.1µF capacitor between pins 26 and 7 is
recommended for decoupling.
GROUND
DATA BUS: The Data Bus lines are bidirectional three-state pins connected to the
system data bus.
RESET: A high on this input clears the control register and all ports (A, B, C) are set
to the input mode with the “Bus Hold” circuitry turned on.
CHIP SELECT: Chip select is an active low input used to enable the 82C55A onto the
Data Bus for CPU communications.
READ: Read is an active low input control signal used by the CPU to read status
information or data via the data bus.
WRITE: Write is an active low input control signal used by the CPU to load control
words and data into the 82C55A.
ADDRESS: These input signals, in conjunction with the RD and WR inputs, control
the selection of one of the three ports or the control word register. A0 and A1 are
normally connected to the least significant bits of the Address Bus A0, A1.
PORT A: 8-bit input and output port. Both bus hold high and bus hold low circuitry are
present on this port.
PORT B: 8-bit input and output port. Bus hold high circuitry is present on this port.
PORT C: 8-bit input and output port. Bus hold circuitry is present on this port.
POWER
SUPPLIES
+5V
GND
GROUP A
CONTROL
BI-DIRECTIONAL
DATA BUS
D7-D0
DATA BUS
BUFFER
RD
WR
A1
A0
RESET
CS
READ
WRITE
CONTROL
LOGIC
8-BIT
INTERNAL
DATA BUS
GROUP B
CONTROL
GROUP A
PORT A
(8)
GROUP A
PORT C
UPPER
(4)
GROUP B
PORT C
LOWER
(4)
GROUP B
PORT B
(8)
I/O
PA7-PA0
I/O
PC7-PC4
I/O
PC3-PC0
I/O
PB7-PB0
2









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WS82C55A-5P Даташит, Описание, Даташиты
WS82C55A
Functional Description
Data Bus Buffer
This three-state bi-directional 8-bit buffer is used to interface
WS82C55A to the system data bus. Data is transmitted or
received by the buffer upon execution of input or output
instructions by the CPU. Control words and status informa-
tion are also transferred through the data bus buffer.
Read/Write and Control Logic
POWER
SUPPLIES
+5V
GND
BI-DIRECTIONAL
DATA BUS
D7-D0
DATA
BUS
BUFFER
GROUP A
CONTROL
8-BIT
INTERNAL
DATA BUS
GROUP A
PORT A
(8)
GROUP A
PORT C
UPPER
(4)
GROUP B
PORT C
LOWER
(4)
I/O
PA7-
PA0
I/O
PC7-
PC4
I/O
PC3-
PC0
The function of this block is to manage all of the internal and
external transfers of both Data and Control or Status words.
It accepts inputs from the CPU Address and Control busses
and in turn, issues commands to both of the Control Groups.
RD
WR
A1
A0
RESET
READ
WRITE
CONTROL
LOGIC
GROUP B
CONTROL
GROUP B
PORT B
(8)
I/O
PB7-
PB0
(CS) Chip Select. A “low” on this input pin enables the
communcation between the WS82C55A and the CPU
(RD) Read. A “low” on this input pin enables 82C55A to send
the data or status information to the CPU on the data bus. In
essence, it allows the CPU to “read from” the WS82C55A
CS
FIGURE 1. 82C55A BLOCK DIAGRAM. DATA BUS BUFFER,
READ/WRITE, GROUP A & B CONTROL LOGIC
FUNCTIONS
(WR) Write. A “low” on this input pin enables the CPU to
write data or control words into the WS82C55A
(A0 and A1) Port Select 0 and Port Select 1. These input
signals, in conjunction with the RD and WR inputs, control
the selection of one of the three ports or the control word
register. They are normally connected to the least significant
bits of the address bus (A0 and A1).
WS 82C55A BASIC OPERATION
A1 A0 RD WR CS
INPUT OPERATION
(READ)
0 0 0 1 0 Port A Data Bus
0 1 0 1 0 Port B Data Bus
1 0 0 1 0 Port C Data Bus
1 1 0 1 0 Control Word Data Bus
OUTPUT OPERATION
(WRITE)
0 0 1 0 0 Data Bus Port A
0 1 1 0 0 Data Bus Port B
(RESET) Reset. A “high” on this input initializes the control
register to 9Bh and all ports (A, B, C) are set to the input
mode. “Bus hold” devices internal to the 82C55A will hold
the I/O port inputs to a logic “1” state with a maximum hold
current of 400µA.
Group A and Group B Controls
The functional configuration of each port is programmed by
the systems software. In essence, the CPU “outputs” a con-
trol word to the WS82C55A . The control word contains
information such as “mode”, “bit set”, “bit reset”, etc., that ini-
tializes the functional configuration of the WS82C55A
Each of the Control blocks (Group A and Group B) accepts
“commands” from the Read/Write Control logic, receives
“control words” from the internal data bus and issues the
proper commands to its associated ports.
Control Group A - Port A and Port C upper (C7 - C4)
Control Group B - Port B and Port C lower (C3 - C0)
The control word register can be both written and read as
shown in the “Basic Operation” table. Figure 4 shows the
control word format for both Read and Write operations.
When the control word is read, bit D7 will always be a logic
“1”, as this implies control word mode information.
1 0 1 0 0 Data Bus Port C
1 1 1 0 0 Data Bus Control
DISABLE FUNCTION
X X X X 1 Data Bus Three-State
X X 1 1 0 Data Bus Three-State
3










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