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ZPSD402A2-C-70J PDF даташит

Спецификация ZPSD402A2-C-70J изготовлена ​​​​«STMicroelectronics» и имеет функцию, называемую «Low Cost Field Programmable Microcontroller Peripherals».

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Номер произв ZPSD402A2-C-70J
Описание Low Cost Field Programmable Microcontroller Peripherals
Производители STMicroelectronics
логотип STMicroelectronics логотип 

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ZPSD402A2-C-70J Даташит, Описание, Даташиты
PSD4XX
ZPSD4XX
Low Cost Field Programmable Microcontroller Peripherals
NOT FOR NEW DESIGN
FEATURES SUMMARY
s Single Supply Voltage:
– 5 V±10% for PSD4XX
– 2.7 to 5.5 V for PSD4XX-V
s Up to 1 Mbit of UV EPROM
s Up to 16 Kbit SRAM
s Input Latches
s Programmable I/O ports
s Page Logic
s Programmable Security
Figure 1. Packages
PLDCC68 (J)
CLDCC68 (L)
TQFP68 (U)
January 2002
This is information on a product still in production but not recommended for new designs.
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ZPSD402A2-C-70J Даташит, Описание, Даташиты
PSD4XX Family
PSD4XX/ZPSD4XX
Field-Programmable Microcontroller Peripherals
Table of Contents
1 Introduction ...........................................................................................................................................................1
2 Key Features ........................................................................................................................................................2
3 Notation ................................................................................................................................................................3
4 Zero-Power Background .......................................................................................................................................3
5 Integrated Power ManagementTM Operation ........................................................................................................5
6 Design Flow ..........................................................................................................................................................6
7 PSD4XX Family ....................................................................................................................................................7
8 Table 2. PSD4XX Pin Descriptions......................................................................................................................8
9 The PSD4XX Architecture ..................................................................................................................................10
9.1 The ZPLD Block..........................................................................................................................................10
9.1.1 The PSD4XXA1 ZPLD Block............................................................................................................10
9.1.1.1 The DPLD ..........................................................................................................................12
9.1.1.2 The GPLD ..........................................................................................................................13
9.1.1.3 TPA Macrocell Structure ...................................................................................................13
9.1.1.4 Port B Macrocell Structure .................................................................................................17
9.1.1.5 The ZPLD Power Management..........................................................................................18
9.1.2 The PSD4XXA2 ZPLD Block............................................................................................................22
9.1.2.1 The DPLD ..........................................................................................................................24
9.1.2.2 The GPLD ..........................................................................................................................26
9.1.2.3 Port A Macrocell Structure .................................................................................................26
9.1.2.4 Port B Macrocell Structure .................................................................................................30
9.1.2.5 Port E Macrocell Structure .................................................................................................33
9.1.2.6 The ZPLD Power Management..........................................................................................34
9.2 Bus Interface...............................................................................................................................................37
9.2.1 Bus Interface Configuration ..............................................................................................................37
9.2.2 PSD4XX Interface to a Multiplexed Bus ...........................................................................................38
9.2.3 PSD4XX Interface to Non-Multiplexed Bus ......................................................................................38
9.2.4 Data Byte Enable..............................................................................................................................42
9.2.5 Optional Features .............................................................................................................................43
9.2.6 Bus Interface Examples....................................................................................................................43
9.3 I/O Ports......................................................................................................................................................48
9.3.1 Standard MCU I/O ............................................................................................................................48
9.3.2 PLD I/O ...........................................................................................................................................48
9.3.3 Address Out......................................................................................................................................49
9.3.4 Address In ........................................................................................................................................49
9.3.5 Data Port ..........................................................................................................................................49
9.3.6 Alternate Function In ........................................................................................................................49
9.3.7 Peripheral I/O ...................................................................................................................................50
9.3.8 Open Drain Outputs..........................................................................................................................50
9.3.9 Port Registers...................................................................................................................................51
9.3.10 Port A – Functionality and Structure.................................................................................................54
9.3.11 Port B – Functionality and Structure.................................................................................................54
9.3.12 Port C and Port D – Functionality and Structure ..............................................................................57
9.3.13 Port E – Functionality and Structure.................................................................................................57
9.4 Memory Block .............................................................................................................................................61
9.4.1 EPROM ............................................................................................................................................61
9.4.2 SRAM ...............................................................................................................................................61
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ZPSD402A2-C-70J Даташит, Описание, Даташиты
PSD4XX Family
PSD4XX/ZPSD4XX
Field-Programmable Microcontroller Peripherals
Table of Contents (cont.)
9.4.3 Memory Select Map..........................................................................................................................61
9.4.4 Memory Select Map for 8031 Application.........................................................................................62
9.4.5 Peripheral I/O ...................................................................................................................................65
9.5 Power Management Unit ............................................................................................................................67
9.5.1 Standby Mode ..................................................................................................................................67
9.5.2 Other Power Saving Options ............................................................................................................70
10.0 Page Register .....................................................................................................................................................72
11.0 Security Protection..............................................................................................................................................72
12.0 System Configuration .........................................................................................................................................73
12.1 Reset Input ..............................................................................................................................................76
12.2 ZPLD and Memory During Reset.............................................................................................................76
12.3 Register Values During and After Reset..................................................................................................76
12.4 ZPLD Macrocell Initialization ...................................................................................................................76
13.0 Specifications......................................................................................................................................................77
13.1 Absolute Maximum Ratings .....................................................................................................................77
13.2 Operating Range .....................................................................................................................................77
13.3 Recommended Operating Conditions......................................................................................................77
13.4 AC/DC Parameters ..................................................................................................................................78
13.5 Example of ZPSD4XX Typical Power Calculation at VCC = 5.0 V...........................................................80
13.6 DC Characteristics (5 V ± 10% versions) ................................................................................................81
13.7 AC/DC Parameters – ZPLD Timing Parameters .....................................................................................82
13.8 Microcontroller Interface – AC/DC Parameters .......................................................................................84
13.9 DC Characteristics (ZPSD4XXV Versions) (3.0 V ± 10% versions) ........................................................88
13.10 AC/DC Parameters – ZPLD Timing Parameters (3.0 V ± 10% versions)................................................89
13.11 Microcontroller Interface – AC/DC Parameters (3.0 V± 10% versions)...................................................91
14.0 Timing Diagrams.................................................................................................................................................95
15.0 Pin Capacitance................................................................................................................................................102
16.0 AC Testing ........................................................................................................................................................102
17.0 Erasure and Programming................................................................................................................................102
18.0 PSD4XX Pin Assignments ................................................................................................................................103
19.0 Package Information.........................................................................................................................................105
20.0 PSD4XX Product Ordering Information ............................................................................................................110
20.1 PSD4XX Family – Selector Guide .........................................................................................................110
20.2 Part Number Construction .....................................................................................................................111
20.3 Ordering Information..............................................................................................................................111
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Номер в каталогеОписаниеПроизводители
ZPSD402A2-C-70JLow Cost Field Programmable Microcontroller PeripheralsSTMicroelectronics
STMicroelectronics
ZPSD402A2-C-70LLow Cost Field Programmable Microcontroller PeripheralsSTMicroelectronics
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ZPSD402A2-C-70ULow Cost Field Programmable Microcontroller PeripheralsSTMicroelectronics
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