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ZXFV4583 PDF даташит

Спецификация ZXFV4583 изготовлена ​​​​«Zetex Semiconductors» и имеет функцию, называемую «SYNC SEPARATOR WITH VARIABLE FILTER».

Детали детали

Номер произв ZXFV4583
Описание SYNC SEPARATOR WITH VARIABLE FILTER
Производители Zetex Semiconductors
логотип Zetex Semiconductors логотип 

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ZXFV4583 Даташит, Описание, Даташиты
SYNC SEPARATOR WITH VARIABLE FILTER
ZXFV4583
DEVICE DESCRIPTION
The ZXFV4583 provides the ability to separate out
video synchronization signals for a wide variety of TV
and CRT display systems, standard and non-standard.
Flexibility arises from the use of just three external
resistors to adapt to each application. One resistor
controls a fully integrated internal color carrier filter
with variable bandwidth. This filter avoids disturbance
from the color carrier, permitting accurate threshold
slicing for timing extraction.
A second resistor controls the voltage threshold for
loss of signal detection after a time-out interval. The
third resistor controls the timing functions.
FEATURES AND BENEFITS
PAL, NTSC, SECAM
Variable filter for optimal accuracy
Sync outputs: composite, horizontal, vertical, back
porch, odd/even
No-signal detector
On chip sample / hold capacitors
+5V single supply
Default vertical output where there are no
serration pulses
Pin and layout compatible with part EL4583 in
SO16N surface mount package
DC restoration for displays is facilitated by the Back
Porch synch output, which can be used to drive an
external circuit to clamp the blanking voltage to a fixed
level.
ORDERING INFORMATION
Part Number
Container
ZXFV4583N16TA
Reel 7
ZXFV4583N16TC
Reel 13
Increment
500
2500
APPLICATIONS
Digital image capture
Video input systems requiring separation of
picture timing
Video distribution
CCTV surveillance
Digital multimedia
Timing for black level clamp
CONNECTION DIAGRAM
ISSUE 3 - NOVEMBER 2003
1
SEMICONDUCTORS









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ZXFV4583 Даташит, Описание, Даташиты
ZXFV4583
ABSOLUTE MAXIMUM RATINGS
Supply voltage VCC
Inputs to ground*
Operating temperature range
-0.5V to +7V
-0.5V to VCC +0.5V
-40ЊC to 85ЊC
Storage
-65ЊC to +150ЊC
Operating ambient junction temperature
TJMAX150ЊC**
**The thermal resistance from the semiconductor die to ambient is typically 120ЊC/W when the SO16 package is
mounted on a PCB in free air. The power dissipation of the device when loaded must be designed to keep the
device junction temperature below TJMAX.
*During power-up and power-down, these voltage ratings require that signals be applied only when the power
supply is connected.
ELECTRICAL CHARACTERISTICS
VCC = 5V, RSET = 681k, RFILT = 22k, RNOSIG = 82k, Tamb = 25ЊC unless otherwise stated.
Test level:
P = 100% production test
C = Characterized only
PARAMETER
DC Characteristics
Supply current
Clamp voltage at FILTIN
Discharge current at FILTIN
Discharge current at FILTIN
Clamp charge current at FILTIN
Clamp voltage at FVIDIN
Discharge current at FVIDIN
Discharge current at FVIDIN
Clamp charge current at FVIDIN
RSET voltage, pin 12
RFILT voltage, pin 1
RNOSIG current, pin 2
Logic output low voltage, VOL
CONDITIONS
Pin 4 unloaded
Pin 4, Vin = 2V pk-pk
Pin 4, no signal
Pin 4, Vin = 1V pk-pk
Pin 8 unloaded
Pin 8, Vin = 2V pk-pk
Pin 8, no signal
Pin 8, Vin = 1V pk-pk
IOL = 1.6mA
TEST MIN TYP MAX UNIT
P 2 4.5 6.5 mA
P 1.2 1.35 1.5 V
C 1 A
C 3 6 12 A
P 2 3 4 mA
P 1.2 1.35 1.5 V
C 1 ␮〈
C 3 6 12 ␮〈
P 2 3 4 mA
P 1.5 1.75 2 V
P 0.35 0.5 0.65 V
P 1.5 2.5 3.5 A
P 0.35 0.8 V
SEMICONDUCTORS
ISSUE 3 - NOVEMBER 2003
2









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ZXFV4583 Даташит, Описание, Даташиты
ZXFV4583
ELECTRICAL CHARACTERISTICS (Cont.)
VCC = 5V, RSET = 681k, RFILT = 22k, RNOSIG = 82k, Tamb = 25ЊC unless otherwise stated.
PARAMETER
AC Characteristics
FILTIN function input voltage range
Filter voltage gain
Filter attenuation
Slice level
CSYNC prop. Delay, tCS
VSYNC delay
VSYNC pulse width, tVSYNC (PAL)
VSYNC pulse width, tVSYNC (NTSC)
VSYNC default delay, tVSD
HSYNC delay
HSYNC pulse width, tHSYNC
BKPCH delay, tBD
BKPCH pulse width, tB
CONDITIONS
PAL/NTSC
FILTIN to FILOUT
4.4MHz for PAL,
3.6MHz for NTSC
Vin = 1V pk-pk
Relative to pin 4 input
Relative to pin 4 input
TEST MIN TYP MAX UNIT
P 0.5
2 V pk-pk
P 4.9 5.7 6.5
dB
P 15 19
P 10 14
dB
dB
P 40 50
60
%
P
250 400
ns
C 250
ns
C 165
s
C 195
s
P 30 36 45
s
P 250
ns
P 3.8 5 6.2
s
P
250 400
ns
P 2.7 3.7 4.7
s
Note:
In order to avoid coupling between high speed logic output signals and analog inputs, the test circuit
layout uses connections from the logic output pins routed away from the analog pins. In the application,
similar care in the layout is required, keeping resistors RFILT, RNOSIG and RSET close to their respective
pins, in particular routing signal CSYNC away from pins 1, 2 and 12.
ISSUE 3 - NOVEMBER 2003
3
SEMICONDUCTORS










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