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GS81032AT PDF даташит

Спецификация GS81032AT изготовлена ​​​​«GSI Technology» и имеет функцию, называемую «32K x 32 / 1M Synchronous Burst SRAM».

Детали детали

Номер произв GS81032AT
Описание 32K x 32 / 1M Synchronous Burst SRAM
Производители GSI Technology
логотип GSI Technology логотип 

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GS81032AT Даташит, Описание, Даташиты
GS81032AT/Q-150/138/133/117/100/66
TQFP, QFP
Commercial Temp
Industrial Temp
32K x 32
1M Synchronous Burst SRAM
150 MHz–66 MHz
9 ns–18 ns
3.3 V VDD
3.3 V and 2.5 V I/O
Features
• FT pin for user-configurable flow through or pipeline
operation
• Single Cycle Deselect (SCD) operation
• 3.3 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Common data inputs and data outputs
• Clock Control, registered, address, data, and control
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP or QFP package
-150 -138 -133 -117 -100 -66 Unit
Pipeline tCycle 6.6 7.25 7.5 8.5 10 12.5 ns
3-1-1-1 tKQ 3.8 4 4 4.5 5 6 ns
IDD 270 245 240 210 180 150 mA
Flow tCycle 10.5 15 15 15 15 20 ns
Through tKQ 9 9.7 10 11 12 18 ns
2-1-1-1 IDD 170 120 120 120 120 95 mA
Functional Description
Applications
The GS81032A is a 1,048,576-bit high performance
synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications,
ranging from DSP main store to networking chip set support.
Controls
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
SCD Pipelined Reads
The GS81032A is an SCD (Single Cycle Deselect) pipelined
synchronous SRAM. DCD (Dual Cycle Deselect) versions are
also available. SCD SRAMs pipeline deselect commands one
stage less than read commands. SCD RAMs begin turning off
their outputs immediately after the deselect command has been
captured in the input registers.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the byte write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(high) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS81032A operates on a 3.3 V power supply and all
inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate
output power (VDDQ) pins are used to decouple output noise
from the internal circuit.
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Rev: 1.01 7/2001
1/23 © 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.









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GS81032AT Даташит, Описание, Даташиты
GS81032A 100-Pin TQFP and QFP Pinout
GS81032AT/Q-150/138/133/117/100/66
NC
DQC8
DQC7
VDDQ
VSS
DQC6
DQC5
DQC4
DQC3
VSS
VDDQ
DQC2
DQC1
FT
VDD
NC
VSS
DQD1
DQD2
VDDQ
VSS
DQD3
DQD4
DQD5
DQD6
VSS
VDDQ
DQD7
DQD8
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1 80
2 79
3 78
4 77
5 76
6 75
7 74
8 73
9
10
32K x 32
72
71
11 Top View
70
12 69
13 68
14 67
15 66
16 65
17 64
18 63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
DQB8
DQB7
VDDQ
VSS
DQB6
DQB5
DQB4
DQB3
VSS
VDDQ
DQB2
DQB1
VSS
NC
VDD
ZZ
DQA1
DQA2
VDDQ
VSS
DQA3
DQA4
DQA5
DQA6
VSS
VDDQ
DQA7
DQA8
NC
Rev: 1.01 7/2001
2/23 © 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.









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GS81032AT Даташит, Описание, Даташиты
TQFP Pin Description
Pin Location
Symbol
37, 36
35, 34, 33, 32, 100, 99, 82, 81, 44, 45,
46, 47, 48
A0, A1
A2–A14
52, 53, 56, 57, 58, 59, 62, 63
68, 69, 72, 73, 74, 75, 78, 79
2, 3, 6, 7, 8, 9, 12, 13
18, 19, 22, 23, 24, 25, 28, 29
16, 38, 39, 42, 43, 66, 50, 51,
80, 1, 30, 49
DQA1–DQA8
DQB1–DQB8
DQC1–DQC8
DQD1–DQD8
NC
87 BW
93, 94
95, 96
89
BA, BB
BC, BD
CK
88 GW
98, 92
97
86
E1, E3
E2
G
83 ADV
84, 85
ADSP, ADSC
64 ZZ
14 FT
31 LBO
15, 41, 65, 91
5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90
4, 11, 20, 27, 54, 61, 70, 77
VDD
VSS
VDDQ
Type
I
I
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
GS81032AT/Q-150/138/133/117/100/66
Description
Address field LSBs and Address Counter preset Inputs
Address Inputs
Data Input and Output pins
No Connect
Byte Write—Writes all enabled bytes; active low
Byte Write Enable for DQA, DQB Data I/Os; active low
Byte Write Enable for DQC, DQD Data I/Os; active low
Clock Input Signal; active high
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
Chip Enable; active high
Output Enable; active low
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Sleep Mode control; active high
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Core power supply
I/O and core ground
Output driver power supply
Rev: 1.01 7/2001
3/23 © 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.










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