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74HCT40103 PDF даташит

Спецификация 74HCT40103 изготовлена ​​​​«Integrated Circuit Systems» и имеет функцию, называемую «8-bit synchronous binary down counter».

Детали детали

Номер произв 74HCT40103
Описание 8-bit synchronous binary down counter
Производители Integrated Circuit Systems
логотип Integrated Circuit Systems логотип 

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74HCT40103 Даташит, Описание, Даташиты
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT40103
8-bit synchronous binary down
counter
Product specification
Supersedes data of December 1990
File under Integrated Circuits, IC06
1998 Jul 08









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74HCT40103 Даташит, Описание, Даташиты
Philips Semiconductors
8-bit synchronous binary down counter
Product specification
74HC/HCT40103
FEATURES
Cascadable
Synchronous or asynchronous preset
Output capability: standard
ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT40103 are high-speed Si-gate CMOS
devices and are pin compatible with the “40103” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT40103 consist each of an 8-bit
synchronous down counter with a single output which is
active when the internal count is zero. The “40103”
contains a single 8-bit binary counter and has control
inputs for enabling or disabling the clock (CP), for clearing
the counter to its maximum count, and for presetting the
counter either synchronously or asynchronously. All
control inputs and the terminal count output (TC) are
active-LOW logic.
In normal operation, the counter is decremented by one
count on each positive-going transition of the clock (CP).
Counting is inhibited when the terminal enable input (TE)
is HIGH. The terminal count output (TC) goes LOW when
the count reaches zero if TE is LOW, and remains LOW for
one full clock period.
When the synchronous preset enable input (PE) is LOW,
data at the jam input (P0 to P7) is clocked into the counter
on the next positive-going clock transition regardless of the
state of TE. When the asynchronous preset enable input
(PL) is LOW, data at the jam input (P0 to P7) is
asynchronously forced into the counter regardless of the
state of PE, TE, or CP. The jam inputs (P0 to P7) represent
a single 8-bit binary word.
When the master reset input (MR) is LOW, the counter is
asynchronously cleared to its maximum count (decimal
255) regardless of the state of any other input. The
precedence relationship between control inputs is
indicated in the function table.
If all control inputs except TE are HIGH at the time of zero
count, the counters will jump to the maximum count, giving
a counting sequence of 256 clock pulses long.
The “40103” may be cascaded using the TE input and the
TC output, in either a synchronous or ripple mode.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
SYMBOL PARAMETER
CONDITIONS
tPHL/ tPLH
fmax
CI
CPD
propagation delay CP to TC
maximum clock frequency
input capacitance
power dissipation capacitance per package
CL = 15 pF; VCC = 5 V
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
(CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC 1.5 V
TYPICAL
HC
30
32
3.5
24
HCT
30
31
3.5
27
UNIT
ns
MHz
pF
pF
1998 Jul 08
2









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74HCT40103 Даташит, Описание, Даташиты
Philips Semiconductors
8-bit synchronous binary down counter
Product specification
74HC/HCT40103
ORDERING INFORMATION
TYPE NUMBER
NAME
PACKAGE
DESCRIPTION
74HC40103N;
74HCT40103N
DIP16 plastic dual in-line package; 16 leads (300 mil); long body
74HC40103D;
74HCT40103D
SO16 plastic small outline package; 16 leads; body width 3.9 mm
74HC40103DB; SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm
74HCT40103DB
74HC40103PW; TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm
VERSION
SOT38-1
SOT109-1
SOT338-1
SOT403-1
PIN DESCRIPTION
PIN NO.
1
2
3
4, 5, 6, 7, 10, 11, 12, 13
8
9
14
15
16
SYMBOL
CP
MR
TE
P0 to P7
GND
PL
TC
PE
VCC
NAME AND FUNCTION
clock input (LOW-to-HIGH, edge-triggered)
asynchronous master reset input (active LOW)
terminal enable input
jam inputs
ground (0 V)
asynchronous preset enable input (active LOW)
terminal count output (active LOW)
synchronous preset enable input (active LOW)
positive supply voltage
Fig.1 Pin configuration.
1998 Jul 08
Fig.2 Logic symbol.
3
Fig.3 IEC logic symbol.










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