74HCT4053 PDF даташит
Спецификация 74HCT4053 изготовлена «Philips» и имеет функцию, называемую «Triple 2-channel analog multiplexer/demultiplexer». |
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Детали детали
Номер произв | 74HCT4053 |
Описание | Triple 2-channel analog multiplexer/demultiplexer |
Производители | Philips |
логотип |
30 Pages
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74HC4053; 74HCT4053
Triple 2-channel analog multiplexer/demultiplexer
Rev. 04 — 9 May 2006
Product data sheet
1. General description
The 74HC4053; 74HCT4053 is a high-speed Si-gate CMOS device and is pin compatible
with the HEF4053B. It is specified in compliance with JEDEC standard no. 7A.
The 74HC4053; 74HCT4053 is triple 2-channel analog multiplexer/demultiplexer with a
common enable input (E). Each multiplexer/demultiplexer has two independent
inputs/outputs (nY0 and nY1), a common input/output (nZ) and three digital select
inputs (Sn).
With E LOW, one of the two switches is selected (low-impedance ON-state) by S1 to S3.
With E HIGH, all switches are in the high-impedance OFF-state, independent of S1 to S3.
VCC and GND are the supply voltage pins for the digital control inputs (S1 to S3 and E).
The VCC to GND ranges are 2.0 V to 10.0 V for 74HC4053 and 4.5 V to 5.5 V for
74HCT4053. The analog inputs/outputs (nY0 and nY1, and nZ) can swing between VCC
as a positive limit and VEE as a negative limit. VCC − VEE may not exceed 10.0 V.
For operation as a digital multiplexer/demultiplexer, VEE is connected to GND (typically
ground).
2. Features
s Low ON resistance:
x 80 Ω (typical) at VCC − VEE = 4.5 V
x 70 Ω (typical) at VCC − VEE = 6.0 V
x 60 Ω (typical) at VCC − VEE = 9.0 V
s Logic level translation:
x To enable 5 V logic to communicate with ±5 V analog signals
s Typical ‘break before make’ built in
s Complies with JEDEC standard no. 7A
s ESD protection:
x HBM EIA/JESD22-A114-C exceeds 2000 V
x MM EIA/JESD22-A115-A exceeds 200 V
s Multiple package options
s Specified from −40 °C to +85 °C and from −40 °C to +125 °C
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Philips Semiconductors
74HC4053; 74HCT4053
Triple 2-channel analog multiplexer/demultiplexer
3. Applications
s Analog multiplexing and demultiplexing
s Digital multiplexing and demultiplexing
s Signal gating
4. Quick reference data
74HC_HCT4053_4
Product data sheet
Table 1: Quick reference data
VEE = GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns.
Symbol Parameter
Conditions
Min Typ Max Unit
74HC4053
tPZH,
tPZL
tPHZ,
tPLZ
Ci
CS
turn-ON time
E to Vos
Sn to Vos
turn-OFF time
E to Vos
Sn to Vos
input capacitance
CL = 15 pF; RL = 1 kΩ;
VCC = 5 V
CL = 15 pF; RL = 1 kΩ;
VCC = 5 V
switch capacitance
independent I/O (nYn)
- 17 - ns
- 21 - ns
- 18 - ns
- 17 - ns
- 3.5 - pF
- 5 - pF
common I/O (nZ)
- 8 - pF
CPD power dissipation
capacitance
74HCT4053
per switch; VI = GND to
VCC
[1] -
36 -
pF
tPZH,
tPZL
tPHZ,
tPLZ
Ci
CS
turn-ON time
E to Vos
Sn to Vos
turn-OFF time
E to Vos
Sn to Vos
input capacitance
CL = 15 pF; RL = 1 kΩ;
VCC = 5 V
CL = 15 pF; RL = 1 kΩ;
VCC = 5 V
switch capacitance
independent I/O (nYn)
- 23 - ns
- 21 - ns
- 20 - ns
- 19 - ns
- 3.5 - pF
- 5 - pF
common I/O(nZ)
- 8 - pF
CPD power dissipation
capacitance
per switch; VI = GND to
(VCC − 1.5 V)
[1] -
36 -
pF
[1] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + ∑{(CL + CS) × VCC2 × fo} where:
fi = input frequency in MHz;
fo = output frequency in MHz;
∑{(CL + CS) × VCC2 × fo} = sum of outputs;
Rev. 04 — 9 May 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
2 of 33
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Philips Semiconductors
74HC4053; 74HCT4053
Triple 2-channel analog multiplexer/demultiplexer
CL = output load capacitance in pF;
CS = maximum switch capacitance in pF;
VCC = supply voltage in V.
5. Ordering information
Table 2: Ordering information
Type number Package
Temperature range Name
Description
74HC4053
74HC4053N −40 °C to +125 °C DIP16
plastic dual in-line package; 16 leads (300 mil); long
body
74HC4053D −40 °C to +125 °C SO16
plastic small outline package; 16 leads; body width
3.9 mm
74HC4053DB −40 °C to +125 °C SSOP16
plastic shrink small outline package; 16 leads; body
width 5.3 mm
74HC4053PW −40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
74HC4053BQ −40 °C to +125 °C
DHVQFN16 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 16 terminals;
body 2.5 × 3.5 × 0.85 mm
74HCT4053
74HCT4053N −40 °C to +125 °C DIP16
plastic dual in-line package; 16 leads (300 mil); long
body
74HCT4053D −40 °C to +125 °C SO16
plastic small outline package; 16 leads; body width
3.9 mm
74HCT4053DB −40 °C to +125 °C SSOP16
plastic shrink small outline package; 16 leads; body
width 5.3 mm
74HCT4053PW −40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
74HCT4053BQ −40 °C to +125 °C
DHVQFN16 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 16 terminals;
body 2.5 × 3.5 × 0.85 mm
Version
SOT38-4
SOT109-1
SOT338-1
SOT403-1
SOT763-1
SOT38-4
SOT109-1
SOT338-1
SOT403-1
SOT763-1
74HC_HCT4053_4
Product data sheet
Rev. 04 — 9 May 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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