74HCT4516 PDF даташит
Спецификация 74HCT4516 изготовлена «Philips» и имеет функцию, называемую «Binary up/down counter». |
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Детали детали
Номер произв | 74HCT4516 |
Описание | Binary up/down counter |
Производители | Philips |
логотип |
14 Pages
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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT4516
Binary up/down counter
Product specification
File under Integrated Circuits, IC06
December 1990
No Preview Available ! |
Philips Semiconductors
Binary up/down counter
Product specification
74HC/HCT4516
FEATURES
• Output capability: standard
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4516 are high-speed Si-gate CMOS
devices and are pin compatible with the “4516” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT4516 are edge-triggered synchronous
up/down 4-bit binary counters with a clock input (CP), an
up/down count control input (UP/DN), an active LOW
count enable input (CE), an asynchronous active HIGH
parallel load input (PL), four parallel inputs (D0 to D3), four
parallel outputs (Q0 to Q3), an active LOW terminal count
output (TC), and an overriding asynchronous master reset
input (MR).
Information on D0 to D3 is loaded into the counter while PL
is HIGH, independent of all other input conditions except
the MR input, which must be LOW. When PL and CE are
LOW, the counter changes on the LOW-to-HIGH transition
of CP. UP/DN determines the direction of the count, HIGH
for counting up, LOW for counting down. When counting
up, TC is LOW when Q0 to Q3 are HIGH and CE is LOW.
When counting down, TC is LOW when Q0 to Q3 and CE
are LOW. A HIGH on MR resets the counter (Q0 to
Q3 = LOW) independent of all other input conditions.
Logic equation for terminal count:
TC = CE . {(UP/DN) . Q0 . Q1 . Q2 . Q3 + (UP ⁄ DN) . Q0 . Q1 . Q2 . Q3}
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
HC HCT
tPHL/ tPLH
fmax
CI
CPD
propagation delay CP to Qn
maximum clock frequency
input capacitance
power dissipation capacitance per package
19
CL = 15 pF; VCC = 5 V 45
3.5
notes 1 and 2
59
19
57
3.5
61
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
UNIT
ns
MHz
pF
pF
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
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Philips Semiconductors
Binary up/down counter
Product specification
74HC/HCT4516
PIN DESCRIPTION
PIN NO.
1
4, 12, 13, 3
5
6, 11, 14, 2
7
8
9
10
15
16
SYMBOL
PL
D0 to D3
CE
Q0 to Q3
TC
GND
MR
UP/DN
CP
VCC
NAME AND FUNCTION
parallel load input (active HIGH)
parallel inputs
count enable input (active LOW)
parallel outputs
terminal count output (active LOW)
ground (0 V)
asynchronous master reset input (active HIGH)
up/down control input
clock input (LOW-to-HIGH, edge-triggered)
positive supply voltage
Fig.1 Pin configuration.
Fig.2
Fig.3 IEC logic symbol.
December 1990
3
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