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74HCT670 PDF даташит

Спецификация 74HCT670 изготовлена ​​​​«Philips» и имеет функцию, называемую «4 x 4 register file; 3-state».

Детали детали

Номер произв 74HCT670
Описание 4 x 4 register file; 3-state
Производители Philips
логотип Philips логотип 

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74HCT670 Даташит, Описание, Даташиты
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT670
4 x 4 register file; 3-state
Product specification
File under Integrated Circuits, IC06
December 1990









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74HCT670 Даташит, Описание, Даташиты
Philips Semiconductors
4 x 4 register file; 3-state
Product specification
74HC/HCT670
FEATURES
Simultaneous and independent read and write
operations
Expandable to almost any word size and bit length
Output capability: bus driver
ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT670 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT670 are 16-bit 3-state register files
organized as 4 words of 4 bits each. Separated read and
write address inputs (RA, RB and WA, WB) and enable
inputs (RE and WE) are available, permitting simultaneous
writing into one word location and reading from another
location. The 4-bit word to be stored is presented to four
data inputs (D0 to D3). The WA and WB inputs determine
the location of the stored word. When the WE input is
LOW, the data is entered into the addressed location. The
addressed location remains transparent to the data while
the WE input is LOW. Data supplied at the inputs will be
read out in true (non-inverting) form from the 3-state
outputs (Q0 to Q3). Dn and Wn inputs are inhibited when
WE is HIGH.
Direct acquisition of data stored in any of the four registers
is made possible by individual read address inputs
(RA and RB). The addressed word appears at the four
outputs when the RE is LOW. Data outputs are in the high
impedance OFF-state when RE is HIGH. This permits
outputs to be tied together to increase the word capacity to
very large numbers.
Design of the read enable signals for the stacked devices
must ensure that there is no overlap in the LOW levels
which would cause more than one output to be active at
the same time. Parallel expansion to generate n-bit words
is accomplished by driving the enable and address inputs
of each device in parallel.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
SYMBOL PARAMETER
CONDITIONS
tPHL/ tPLH
CI
CPD
propagation delay Dn to Qn
input capacitance
power dissipation capacitance per package
CL = 15 pF; VCC = 5 V
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo)
where:
fi = input frequency in MHz
fo = output frequency in MHz
(CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC;
for HCT the condition is VI = GND to VCC 1.5 V
TYPICAL
HC
23
3.5
122
HCT
23
3.5
124
UNIT
ns
pF
pF
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2









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74HCT670 Даташит, Описание, Даташиты
Philips Semiconductors
4 x 4 register file; 3-state
PIN DESCRIPTION
PIN NO.
5, 4
8
10, 9, 7, 6
11
12
14, 13
15, 1, 2, 3
16
SYMBOL
RA, RB
GND
Q0 to Q3
RE
WE
WA, WB
D0 to D3
VCC
NAME AND FUNCTION
read address inputs
ground (0 V)
data outputs
3-state output read enable input (active LOW)
write enable input (active LOW)
write address inputs
data inputs
positive supply voltage
Product specification
74HC/HCT670
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
Fig.4 Functional diagram.
WRITE MODE SELECT TABLE
OPERATING
MODE
write data
data latched
INPUTS
WE Dn
LL
LH
HX
INTERNAL
LATCHES(1)
L
H
no change
Note
1. The write address (WA and WB) to the
“internal latches” must be stable while WE is
LOW for conventional operation.
READ MODE SELECT TABLE
OPERATING
MODE
read
disabled
INPUTS
OUTPUT
RE INTERNAL LATCHES(1)
LL
LH
HX
Qn
L
H
Z
Notes
1. The selection of the “internal latches” by read address
(RA and RB) are not constrained by WE or RE operation.
H = HIGH voltage level
L = LOW voltage level
X = don’t care
Z = high impedance OFF-state
December 1990
3










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