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74HCT7403N PDF даташит

Спецификация 74HCT7403N изготовлена ​​​​«Philips» и имеет функцию, называемую «4-Bit x 64-word FIFO register; 3-state».

Детали детали

Номер произв 74HCT7403N
Описание 4-Bit x 64-word FIFO register; 3-state
Производители Philips
логотип Philips логотип 

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74HCT7403N Даташит, Описание, Даташиты
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT7403
4-Bit x 64-word FIFO register;
3-state
Product specification
Supersedes data of October 1990
File under Integrated Circuits, IC06
September 1993









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74HCT7403N Даташит, Описание, Даташиты
Philips Semiconductors
4-Bit x 64-word FIFO register; 3-state
Product specification
74HC/HCT7403
FEATURES
Synchronous or asynchronous
operation
3-state outputs
30 MHz (typical) shift-in and
shift-out rates
Readily expandable in word and bit
dimensions
Pinning arranged for easy board
layout: input pins directly opposite
output pins
Output capability: driver (8 mA)
ICC category: LSI.
APPLICATIONS
High-speed disc or tape controller
Communications buffer.
GENERAL DESCRIPTION
The 74HC/HCT7403 are high-speed
Si-gate CMOS devices. They are
specified in compliance with JEDEC
standard no.7A.
The “7403” is an expandable, First-In
First-Out (FIFO) memory organized
as 64 words by 4 bits. A guaranteed
15 MHz data-rate makes it ideal for
high-speed applications. A higher
data-rate can be obtained in
applications where the status flags
are not used (burst-mode).
With separate controls for shift-in (SI)
and shift-out (SO), reading and
writing operations are completely
independent, allowing synchronous
and asynchronous data transfers.
Additional controls include a
master-reset input (MR), an output
enable input (OE) and flags. The
data-in-ready (DIR) and
data-out-ready (DOR) flags indicate
the status of the device.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns.
SYMBOL
PARAMETER
CONDITIONS
tPHL/tPLH
fmax
CI
CPD
propagation delay SO,
SI to DIR and DOR
maximum clock
frequency
input capacitance
power dissipation
capacitance per
package
CL = 15 pF;
VCC = 5 V
note 1
TYP.
UNIT
HC HCT
15 17 ns
30 30 MHz
3.5 3.5 pF
475 490 pF
Note
1. For HC the condition is VI = GND to VCC.
For HCT the condition is VI = GND to VCC 1.5 V.
ORDERING INFORMATION
EXTENDED
TYPE NUMBER
74HC/HCT7403N
74HC/HCT7403D
PINS
16
16
PACKAGE
PIN POSITION MATERIAL
DIL
SO16L
plastic
plastic
CODE
SOT38Z
SOT162
September 1993
2









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74HCT7403N Даташит, Описание, Даташиты
Philips Semiconductors
4-Bit x 64-word FIFO register; 3-state
Product specification
74HC/HCT7403
PINNING
SYMBOL
OE
DIR
SI
DO to D3
GND
MR
Q3 to Q0
DOR
SO
VCC
PIN DESCRIPTION
1 output enable input (active LOW)
2 data-in-ready output
3 shift-in input (active HIGH)
4, 5, parallel data input
6, 7
8 ground
9 asynchronous master-reset
input (active LOW)
10, 11, data output
12, 13
14 data-out-ready output
15 shift-out input (active LOW)
16 positive supply voltage
handbook, halfpage
OE 1
DIR 2
SI 3
D0 4
D1 5
D2 6
D3 7
GND 8
16 VCC
15 SO
14 DOR
7403
13 Q0
12 Q1
11 Q2
10 Q3
9 MR
MGA672
Fig.1 Pin configuration.
handbook, halfpage
4
5
6
7
3
15
1
OE
D0 Q0
D1 Q1
D2 Q2
D3 Q3
13
12
11
10
SI DOR
SO DIR
MR
14
2
9 MGA674
Fig.2 Logic symbol.
September 1993
handbook, halfpage
1
3
9
15
4
5
6
7
FIFO 64 x 4
EN4
1Z2
[IR] 3
[OR] 6
CTR
1 ( /C2)
CT = 0
5
CT < 64
CT > 0
G1
G5
5Z6
2D 4
2
14
13
12
11
10
MGA676
Fig.3 IEC logic symbol.
3










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