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74HCT7404 PDF даташит

Спецификация 74HCT7404 изготовлена ​​​​«Philips» и имеет функцию, называемую «5-Bit x 64-word FIFO register; 3-state».

Детали детали

Номер произв 74HCT7404
Описание 5-Bit x 64-word FIFO register; 3-state
Производители Philips
логотип Philips логотип 

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74HCT7404 Даташит, Описание, Даташиты
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT7404
5-Bit x 64-word FIFO register;
3-state
Product specification
Supersedes data of October 1990
File under Integrated Circuits, IC06
September 1993









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74HCT7404 Даташит, Описание, Даташиты
Philips Semiconductors
5-Bit x 64-word FIFO register; 3-state
Product specification
74HC/HCT7404
FEATURES
Synchronous or asynchronous operation
3-state outputs
30 MHz (typical) shift-in and shift-out rates
Readily expandable in word and bit dimensions
Pinning arranged for easy board layout: input pins
directly opposite output pins
Output capability: driver (8 mA)
ICC category: LSI.
APPLICATIONS
High-speed disc or tape controller
Communications buffer.
GENERAL DESCRIPTION
The 74HC/HCT7404 are high-speed Si-gate CMOS
devices specified in compliance with JEDEC standard
no.7A.
The “7404” is an expandable, First-In First-Out (FIFO)
memory organized as 64 words by 5 bits. A guaranteed
15 MHz data-rate makes it ideal for high-speed
applications. A higher data-rate can be obtained in
applications where the status flags are not used
(burst-mode).
With separate controls for shift-in (SI) and shift-out (SO),
reading and writing operations are completely
independent, allowing synchronous and asynchronous
data transfers. Additional controls include a master-reset
input (MR), an output enable input (OE) and flags. The
data-in-ready (DIR) and data-out-ready (DOR) flags
indicate the status of the device.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns.
SYMBOL
PARAMETER
CONDITIONS
tPHL/tPLH
fmax
CI
CPD
propagation delay SO, SI to DIR and DOR
maximum clock frequency
input capacitance
power dissipation capacitance per package
Note
1. For HC the condition is VI = GND to VCC.
For HCT the condition is VI = GND to VCC 1.5 V.
CL = 15 pF; VCC = 5 V
note 1
TYP.
HC
15
30
3.5
475
HCT
17
30
3.5
490
UNIT
ns
MHz
pF
pF
ORDERING INFORMATION
EXTENDED
TYPE NUMBER
74HC/HCT7404N
74HC/HCT7404D
PINS
18
20
PACKAGE
PIN POSITION
MATERIAL
DIL
SO20
plastic
plastic
CODE
SOT102
SOT163A
September 1993
2









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74HCT7404 Даташит, Описание, Даташиты
Philips Semiconductors
5-Bit x 64-word FIFO register; 3-state
Product specification
74HC/HCT7404
PINNING (SOT102)
SYMBOL
OE
DIR
SI
DO to D4
GND
MR
Q4 to Q0
DOR
SO
VCC
PIN DESCRIPTION
1 output enable input (active
LOW)
2 data-in-ready output
3 shift-in input (active HIGH)
4, 5, 6, 7, 8 parallel data inputs
9 ground
10 asynchronous master-reset
input (active LOW)
11, 12, 13, data outputs
14, 15
16 data-out-ready output
17 shift-out input (active LOW)
18 positive supply voltage
PINNING (SOT163A)
SYMBOL
OE
DIR
SI
n.c.
D0 to D4
GND
MR
Q4 to Q0
n.c.
DOR
n.c.
VCC
PIN DESCRIPTION
1 output enable input (active
LOW)
2 data-in-ready output
3 shift-in input (active HIGH)
4 not connected
5, 6, 7, 8, 9 parallel data inputs
10 ground
11 asynchronous master-reset
input (active LOW)
12, 13, 14, data outputs
15, 16
17 not connected
18 data-out ready output
19 not connected
20 positive supply voltage
handbook, halfpage
OE 1
DIR 2
SI 3
D0 4
D1 5
D2 6
D3 7
D4 8
GND 9
18 VCC
17 SO
16 DOR
7404
15 Q0
14 Q1
13 Q2
12 Q3
11 Q4
10 MR
MGA670
handbook, halfpage
OE 1
DIR 2
SI 3
n.c. 4
D0 5
D1 6
D2 7
D3 8
D4 9
GND 10
20 VCC
19 SO
18 DOR
17 n.c.
7404
16 Q0
15 Q1
14 Q2
13 Q3
12 Q4
11 MR
MGA671
Fig.1 Pin configuration (SOT102).
Fig.2 Pin configuration (SOT163).
September 1993
3










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