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74HCT74N PDF даташит

Спецификация 74HCT74N изготовлена ​​​​«Philips» и имеет функцию, называемую «Dual D-type flip-flop with set and reset; positive-edge trigger».

Детали детали

Номер произв 74HCT74N
Описание Dual D-type flip-flop with set and reset; positive-edge trigger
Производители Philips
логотип Philips логотип 

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74HCT74N Даташит, Описание, Даташиты
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
74HC/HCT74
Dual D-type flip-flop with set and
reset; positive-edge trigger
Product specification
Supersedes data of September 1993
File under Integrated Circuits, IC06
1998 Feb 23









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74HCT74N Даташит, Описание, Даташиты
Philips Semiconductors
Dual D-type flip-flop with set and reset;
positive-edge trigger
Product specification
74HC/HCT74
FEATURES
Output capability: standard
ICC category: flip-flops
GENERAL DESCRIPTION
The 74HC/HCT74 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT74 are dual positive-edge triggered, D-type
flip-flops with individual data (D) inputs, clock (CP) inputs,
set (SD) and reset (RD) inputs; also complementary Q and
Q outputs.
The set and reset are asynchronous active LOW inputs
and operate independently of the clock input. Information
on the data input is transferred to the Q output on the
LOW-to-HIGH transition of the clock pulse. The D inputs
must be stable one set-up time prior to the LOW-to-HIGH
clock transition for predictable operation.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
SYMBOL
PARAMETER
CONDITIONS
tPHL/ tPLH
fmax
CI
CPD
propagation delay
nCP to nQ, nQ
nSD to nQ, nQ
nRD to nQ, nQ
maximum clock frequency
input capacitance
power dissipation capacitance per flip-flop
CL = 15 pF; VCC = 5 V
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
(CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC 1.5 V
TYPICAL
HC HCT
UNIT
14 15 ns
15 18 ns
16 18 ns
76 59 MHz
3.5 3.5 pF
24 29 pF
1998 Feb 23
2









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74HCT74N Даташит, Описание, Даташиты
Philips Semiconductors
Dual D-type flip-flop with set and reset;
positive-edge trigger
Product specification
74HC/HCT74
ORDERING INFORMATION
TYPE
NUMBER
74HC(T)74N
74HC(T)74D
74HCT74DB
74HCT74PW
PACKAGE
NAME
DESCRIPTION
VERSION
DIP14
SO14
SSOP14
TSSOP14
plastic dual in-line package; 14 leads (300 mil)
SOT27-1
plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1
plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
PIN DESCRIPTION
PIN NO.
1, 13
2, 12
3, 11
4, 10
5, 9
6, 8
7
14
SYMBOL
1RD, 2RD
1D, 2D
1CP, 2CP
1SD, 2SD
1Q, 2Q
1Q, 2Q
GND
VCC
NAME AND FUNCTION
asynchronous reset-direct input (active LOW)
data inputs
clock input (LOW-to-HIGH, edge-triggered)
asynchronous set-direct input (active LOW)
true flip-flop outputs
complement flip-flop outputs
ground (0 V)
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
1998 Feb 23
3










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