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74LCX16543 PDF даташит

Спецификация 74LCX16543 изготовлена ​​​​«Fairchild Semiconductor» и имеет функцию, называемую «Low Voltage 16-Bit Registered Transceiver with 5V Tolerant Inputs and Outputs».

Детали детали

Номер произв 74LCX16543
Описание Low Voltage 16-Bit Registered Transceiver with 5V Tolerant Inputs and Outputs
Производители Fairchild Semiconductor
логотип Fairchild Semiconductor логотип 

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74LCX16543 Даташит, Описание, Даташиты
May 1995
Revised April 1999
74LCX16543
Low Voltage 16-Bit Registered Transceiver with
5V Tolerant Inputs and Outputs
General Description
The LCX16543 contains sixteen non-inverting transceivers
containing two sets of D-type registers for temporary stor-
age of data flowing in either direction. Each byte has sepa-
rate control inputs which can be shorted together for full
16-bit operation. Separate Latch Enable and Output
Enable inputs are provided for each register to permit inde-
pendent input and output control in either direction of data
flow.
The LCX16543 is designed for low voltage (2.5V or 3.3V)
VCC applications with capability of interfacing to a 5V signal
environment.
The LCX16543 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintaining
CMOS low power dissipation.
Features
s 5V tolerant inputs and outputs
s 2.3V–3.6V VCC specifications provided
s 5.2 ns tPD max (VCC = 3.3V), 20 µA ICC max
s Power down high impedance inputs and outputs
s Supports live insertion/withdrawal (Note 1)
s ±24 mA Output Drive (VCC = 3.0V)
s Implements patented noise/EMI reduction circuitry
s Latch-up performance exceeds 500 mA
s ESD performance:
Human Body Model > 2000V
Machine Model > 200V
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to VCC through a pull-up resistor: the minimum value or the
resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number Package Number
Package Description
74LCX16543MEA
MS56A
56-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74LCX16543MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Logic Symbol
© 1999 Fairchild Semiconductor Corporation DS012464.prf
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74LCX16543 Даташит, Описание, Даташиты
Pin Descriptions
Pin Names
Description
OEABn
OEBAn
CEABn
CEBAn
LEABn
LEBAn
A0–A15
B0–B15
A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-B Enable Input (Active LOW)
B-to-A Enable Input (Active LOW)
A-to-B Latch Enable Input (Active LOW)
B-to-A Latch Enable Input (Active LOW)
A-to-B Data Inputs or B-to-A 3-STATE Outputs
B-to-A Data Inputs or A-to-B 3-STATE Outputs
Data I/O Control Table
Inputs
Latch
Status
Output
Buffers
CEABn LEABn OEABn
HXX
XHX
LLX
XXH
LXL
(Byte n)
Latched
Latched
Transparent
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
A-to-B data flow shown; B-to-A flow control is the same, except using CEBAn, LEBAn and OEBAn
(Byte n)
High Z
High Z
Driving
Functional Description
The LCX16543 contains sixteen non-inverting transceivers
with 3-STATE outputs. The device is byte controlled with
each byte functioning identically, but independent of the
other. The control pins may be shorted together to obtain
full 16-bit operation. The following description applies to
each byte. For data flow from A to B, for example, the A-to-
B Enable (CEABn) input must be LOW in order to enter
data from A0–A15 or take data from B0–B15, as indicated in
the Data I/O Control Table. With CEABn LOW, a LOW sig-
nal on the A-to-B Latch Enable (LEABn) input makes the A-
to-B latches transparent; a subsequent LOW-to-HIGH tran-
sition of the LEABn signal puts the A latches in the storage
mode and their outputs no longer change with the A inputs.
With CEABn and OEABn both LOW, the 3-STATE B output
buffers are active and reflect the data present at the output
of the A latches. Control of data flow from B to A is similar,
but using the CEBAn, LEBAn and OEBAn inputs.
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74LCX16543 Даташит, Описание, Даташиты
Logic Diagrams
Byte 1 (0:7)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Byte 2 (8:15)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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Номер в каталогеОписаниеПроизводители
74LCX16543Low Voltage 16-Bit Registered Transceiver with 5V Tolerant Inputs and OutputsFairchild Semiconductor
Fairchild Semiconductor
74LCX16543MEALow Voltage 16-Bit Registered Transceiver with 5V Tolerant Inputs and OutputsFairchild Semiconductor
Fairchild Semiconductor
74LCX16543MTDLow Voltage 16-Bit Registered Transceiver with 5V Tolerant Inputs and OutputsFairchild Semiconductor
Fairchild Semiconductor

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