74LCX16646MTD PDF даташит
Спецификация 74LCX16646MTD изготовлена «Fairchild Semiconductor» и имеет функцию, называемую «Low Voltage 16-Bit Transceiver/Register with 5V Tolerant Inputs and Outputs». |
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Детали детали
Номер произв | 74LCX16646MTD |
Описание | Low Voltage 16-Bit Transceiver/Register with 5V Tolerant Inputs and Outputs |
Производители | Fairchild Semiconductor |
логотип |
10 Pages
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February 1994
Revised April 1999
74LCX16646
Low Voltage 16-Bit Transceiver/Register with 5V Tolerant
Inputs and Outputs
General Description
The LCX16646 contains sixteen non-inverting bidirectional
registered bus transceivers with 3-STATE outputs, provid-
ing multiplexed transmission of data directly from the input
bus or from the internal storage registers. Each byte has
separate control inputs which can be shorted together for
full 16-bit operation.The DIR inputs determine the direction
of data flow through the device. The CPAB and CPBA
inputs load data into the registers on the LOW-to-HIGH
transition (see Functional Description).
The LCX16646 is designed for low voltage (2.5V or 3.3V)
VCC applications with capability of interfacing to a 5V signal
environment.
The LCX16646 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintaining
CMOS low power dissipation.
Features
s 5V tolerant inputs and outputs
s 2.3V–3.6V VCC specifications provided
s 5.2 ns tPD max (VCC = 3.3V), 20 µA ICC max
s Power down high impedance inputs and outputs
s Supports live insertion/withdrawal (Note 1)
s ±24 mA Output Drive (VCC = 3.0V)
s Implements patented noise/EMI reduction circuitry
s Latch-up performance exceeds 500 mA
s ESD performance:
Human Body Model > 2000V
Machine Model > 200V
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to VCC through a pull-up resistor: the minimum value or the
resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number Package Number
Package Description
74LCX16646MEA
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74LCX16646MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
An
Bn
OEn
CPABn, CPBAn
SABn, SBAn
DIRn
Description
Side A Inputs or 3-STATE Outputs
Side B Inputs or 3-STATE Outputs
Output Enable Inputs
Clock Pulse Inputs
Select Inputs
Direction Control Inputs
© 1999 Fairchild Semiconductor Corporation DS012004.prf
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Connection Diagram
Truth Table
(Note 2)
OE1
DIR1
Inputs
CPAB1 CPBA1 SAB1
SBA1
Data I/O
A0–7 B0–7
Output Operation Mode
H X H or L H or L X X
Isolation
H X
X X X Input Input Clock An Data into A Register
H X X
XX
Clock Bn Data Into B Register
L H X X L X
An to Bn—Real Time (Transparent Mode)
LH
X L X Input Output Clock An Data to A Register
L H H or L X H X
LH
XHX
A Register to Bn (Stored Mode)
Clock An Data into A Register and Output to Bn
LL
LL
LL
LL
H = HIGH Voltage Level
L = LOW Voltage Level
X X X
XX
X H or L X
XX
X = Immaterial
= LOW-to-HIGH Transition.
L Bn to An—Real Time (Transparent Mode)
L Output Input Clock Bn Data into B Register
H B Register to An (Stored Mode)
H Clock Bn into B Register and Output to An
Note 2: The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled;
i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs. Also applies to data I/O (A and B: 8-15) and #2 con-
trol pins.
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Logic Diagrams
Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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Номер в каталоге | Описание | Производители |
74LCX16646MTD | Low Voltage 16-Bit Transceiver/Register with 5V Tolerant Inputs and Outputs | Fairchild Semiconductor |
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