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PDF 74LCX32500G Data sheet ( Hoja de datos )
| Número de pieza | 74LCX32500G | |
| Descripción | Low Voltage 36-Bit Universal Bus Transceivers with 5V Tolerant Inputs and Outputs | |
| Fabricantes | Fairchild Semiconductor | |
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April 2001
Revised June 2002
74LCX32500
Low Voltage 36-Bit Universal Bus Transceivers
with 5V Tolerant Inputs and Outputs
General Description
These 36-bit universal bus transceivers combine D-type
latches and D-type flip-flops to allow data flow in transpar-
ent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs.
The LCX32500 is designed for low voltage (2.5V or 3.3V)
VCC applications with the capability of interfacing to a 5V
signal environment.
The LCX32500 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintaining
CMOS low power.
Features
s 5V tolerant inputs and outputs
s 2.3V–3.6V VCC specifications provided
s 6.0 ns tPD max (VCC = 3.3V), 20 µA ICC max
s Power down high impedance inputs and outputs
s Supports live insertion/withdrawal (Note 1)
s ±24 mA output drive (VCC = 3.0V)
s Uses patented noise/EMI reduction circuitry
s Latch-up performance exceeds 500 mA
s ESD performance:
Human body model > 2000V
Machine model > 200V
s Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to VCC and OE tied to GND through a resistor: the minimum
value or the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number Package Number
Package Description
74LCX32500G
(Note 2)(Note 3)
BGA114A 114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Note 2: Ordering code “G” indicates Trays.
Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2002 Fairchild Semiconductor Corporation DS500406
www.fairchildsemi.com
1 page  
DC Electrical Characteristics (Continued)
Symbol
Parameter
ICC Quiescent Supply Current
∆ICC
Increase in ICC per Input
Note 10: Outputs disabled or 3-STATE only.
Conditions
VI = VCC or GND
3.6V ≤ VI, VO ≤ 5.5V (Note 10)
VIH = VCC −0.6V
VCC
(V)
2.3 − 3.6
2.3 − 3.6
2.3 − 3.6
TA = −40°C to +85°C
Min Max
20
±20
500
Units
µA
µA
AC Electrical Characteristics
Symbol
Parameter
fMAX
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPZL
tPZH
tPLZ
tPHZ
tS
tH
tW
Maximum Clock Frequency
Propagation Delay
Bus to Bus
Propagation Delay
Clock to Bus
Propagation Delay
LE to Bus
Output Enable Time
Output Disable Time
Setup Time
Hold Time
Pulse Width
TA = −40°C to +85°C, RL = 500 Ω
VCC = 3.3V ± 0.3V
VCC = 2.7V
VCC = 2.5V ± 0.2V
CL = 50 pF
CL = 50 pF
CL = 30 pF
Min Max Min Max Min Max
170
1.5 6.0 1.5 7.0 1.5 7.2
1.5 6.0 1.5 7.0 1.5 7.2
1.5 6.7 1.5 8.0 1.5 8.4
1.5 6.7 1.5 8.0 1.5 8.4
1.5 7.0 1.5 8.0 1.5 8.4
1.5 7.0 1.5 8.0 1.5 8.4
1.5 7.2 1.5 8.2 1.5 9.4
1.5 7.2 1.5 8.2 1.5 9.4
1.5 7.0 1.5 8.0 1.5 8.4
1.5 7.0 1.5 8.0 1.5 8.4
2.5 2.5 3.0
1.5 1.5 2.0
3.0 3.0 3.5
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Dynamic Switching Characteristics
Symbol
Parameter
VOLP
Quiet Output Dynamic Peak VOL
VOLV
Quiet Output Dynamic Valley VOL
Capacitance
Conditions
CL = 50 pF, VIH = 3.3V, VIL = 0V
CL = 30 pF, VIH = 2.5V, VIL = 0V
CL = 50 pF, VIH = 3.3V, VIL = 0V
CL = 30 pF, VIH = 2.5V, VIL = 0V
VCC
TA = 25°C
Units
(V) Typical
3.3 0.8
2.5 0.6
V
3.3 −0.8
2.5 −0.6
V
Symbol
CIN
CI/O
CPD
Parameter
Input Capacitance
Input/Output Capacitance
Power Dissipation Capacitance
Conditions
VCC = Open, VI = 0V or VCC
VCC = 3.3V, VI = 0V or VCC
VCC = 3.3V, VI = 0V or VCC, f = 10 MHz
Typical
7
8
20
Units
pF
pF
pF
5 www.fairchildsemi.com
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| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet 74LCX32500G.PDF ] | |
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