74LCX32M PDF даташит
Спецификация 74LCX32M изготовлена «Fairchild Semiconductor» и имеет функцию, называемую «Low Voltage Quad 2-Input OR Gate». |
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Детали детали
Номер произв | 74LCX32M |
Описание | Low Voltage Quad 2-Input OR Gate |
Производители | Fairchild Semiconductor |
логотип |
13 Pages
No Preview Available ! |
December 2013
74LCX32
Low Voltage Quad 2-Input OR Gate with 5V Tolerant Inputs
Features
■ 5V tolerant inputs
■ 2.3V–3.6V VCC specifications provided
■ 5.5ns tPD max. (VCC = 3.3V), 10µA ICC max.
■ Power down high impedance inputs and outputs
■ ±24mA output drive (VCC = 3.0V)
■ Implements proprietary noise/EMI reduction circuitry
■ Latch-up performance exceeds JEDEC 78 conditions
■ ESD performance:
– Human body model > 2000V
– Machine model > 150V
■ Leadless DQFN package
General Description
The LCX32 contains four 2-input OR gates. The inputs
tolerate voltages up to 7V allowing the interface of 5V
systems to 3V systems.
The 74LCX32 is fabricated with advanced CMOS tech-
nology to achieve high speed operation while maintain-
ing CMOS low power dissipation.
Ordering Information
Package
Order Number Number
Package Description
74LCX32M
M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74LCX32SJ
74LC32BQX(1)
M14D
MLP14A
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC
MO-241, 2.5 x 3.0mm
74LCX32MTC
MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Note:
1. DQFN package available in Tape and Reel only.
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1995 Fairchild Semiconductor Corporation
74LCX32 Rev. 1.6.1
www.fairchildsemi.com
No Preview Available ! |
Connection Diagrams
Pin Assignments for SOIC, SOP, and TSSOP
Logic Symbol
IEEE/IEC
Pad Assignments for DQFN
(Top View)
(Bottom View)
Pin Description
Pin Names Description
An, Bn
On
DAP
Inputs
Outputs
No Connect
Note: DAP (Die Attach Pad)
©1995 Fairchild Semiconductor Corporation
74LCX32 Rev. 1.6.1
2
www.fairchildsemi.com
No Preview Available ! |
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
VCC
VI
VO
IIK
IOK
IO
ICC
IGND
TSTG
Supply Voltage
DC Input Voltage
DC Output Voltage, Output in HIGH or LOW State(2)
DC Input Diode Current, VI < GND
DC Output Diode Current
VO < GND
VO > VCC
DC Output Source/Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
Note:
2. IO Absolute Maximum Rating must be observed.
Rating
–0.5V to +7.0V
–0.5V to +7.0V
–0.5V to VCC + 0.5V
–50mA
–50mA
+50mA
±50mA
±100mA
±100mA
–65°C to +150°C
Recommended Operating Conditions(3)
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
Parameter
VCC Supply Voltage
Operating
Data Retention
VI
VO
IOH / IOL
TA
∆t / ∆V
Input Voltage
Output Voltage, HIGH or LOW State
Output Current
VCC = 3.0V–3.6V
VCC = 2.7V–3.0V
VCC = 2.3V–2.7V
Free-Air Operating Temperature
Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V
Note:
3. Unused inputs must be held HIGH or LOW. They may not float.
Min.
2.0
1.5
0
0
–40
0
Max.
3.6
3.6
5.5
VCC
±24
±12
±8
85
10
Units
V
V
V
mA
°C
ns /V
©1995 Fairchild Semiconductor Corporation
74LCX32 Rev. 1.6.1
3
www.fairchildsemi.com
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