74LCX374 Datasheet PDF - ST Microelectronics
| Part Number | 74LCX374 | |
| Description | OCTAL D-TYPE FLIP FLOP NON-INVERTING | |
| Manufacturers | ST Microelectronics | |
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74LCX374
OCTAL D-TYPE FLIP FLOP NON-INVERTING (3-STATE)
WITH 5V TOLERANT INPUTS AND OUTPUTS
s 5V TOLERANT INPUTS AND OUTPUTS
s HIGH SPEED:
fMAX = 150 MHz (MIN.) at VCC = 3V
s POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24mA (MIN) at VCC = 3V
s PCI BUS LEVELS GUARANTEED AT 24 mA
SOP
TSSOP
s BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s OPERATING VOLTAGE RANGE:
VCC(OPR) = 2.0V to 3.6V (1.5V Data
Retention)
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 374
Table 1: Order Codes
PACKAGE
SOP
TSSOP
T&R
74LCX374MTR
74LCX374TTR
s LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17)
s ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
DESCRIPTION
The 74LCX374 is a low voltage CMOS OCTAL
D-TYPE FLIP FLOP with 3 STATE OUTPUT
NON-INVERTING fabricated with sub-micron
silicon gate and double-layer metal wiring C2MOS
technology. It is ideal for low power and high
speed 3.3V applications; it can be interfaced to 5V
signal environment for both inputs and outputs.
These 8 bit D-Type flip-flops are controlled by a
clock input (CK) and an output enable input (OE).
On the positive transition of the clock, the Q
outputs will be set to the logic state that were
setup at the D inputs.
While the (OE) input is low, the 8 outputs will be in
a normal logic state (high or low logic level) and
while high level the outputs will be in a high
impedance state.
The Output control does not affect the internal
operation of flip flops; that is, the old data can be
retained or the new data can be entered even
while the outputs are off.
It has same speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
Figure 1: Pin Connection And IEC Logic Symbols
September 2004
Rev. 4
1/13
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74LCX374
Table 8: AC Electrical Characteristics
Test Condition
Value
Symbol
Parameter
tPLH tPHL
tPZL tPZH
tPLZ tPHZ
tS
th
tW
fMAX
tOSLH
tOSHL
Propagation Delay
Time
Output Enable Time
to HIGH and LOW
level
Output Disable Time
from HIGH to LOW
level
Set-Up Time, HIGH
or LOW level
(Dn to CK)
Hold Time, HIGH or
LOW level
(Dn to CK)
CK Pulse Width,
HIGH
Clock Pulse
Frequency
Output To Output
Skew Time (note1,
2)
VCC
(V)
2.7
3.0 to 3.6
2.7
3.0 to 3.6
2.7
3.0 to 3.6
2.7
3.0 to 3.6
2.7
3.0 to 3.6
2.7
3.0 to 3.6
3.0 to 3.6
3.0 to 3.6
CL RL ts = tr
(pF) (Ω) (ns)
50 500 2.5
50 500 2.5
50 500 2.5
50 500 2.5
50 500 2.5
50 500 2.5
50 500 2.5
50 500 2.5
-40 to 85 °C
Min.
1.5
1.5
1.5
Max.
9.5
8.5
9.5
1.5 8.5
1.5 8.5
1.5 7.5
2.5
2.5
1.5
1.5
3.3
3.3
150
1.0
-55 to 125 °C
Min.
1.5
1.5
1.5
Max.
9.5
8.5
9.5
1.5 8.5
1.5 8.5
1.5 7.5
2.5
2.5
1.5
1.5
3.3
3.3
140
1.0
Unit
ns
ns
ns
ns
ns
ns
MHz
ns
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (tOSLH = | tPLHm - tPLHn|, tOSHL = | tPHLm - tPHLn|)
2) Parameter guaranteed by design
Table 4: Capacitive Characteristics
Test Condition
Value
Symbol
Parameter
VCC
(V)
TA = 25 °C
Min. Typ. Max.
Unit
CIN Input Capacitance
3.3 VIN = 0 to VCC
6 pF
COUT Output Capacitance
3.3 VIN = 0 to VCC
12 pF
CPD Power Dissipation Capacitance
(note 1)
3.3
fIN = 10MHz
VIN = 0 or VCC
32
pF
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/8 (per
flip-flop)
5/13
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| Information | Total 13 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ 74LCX374.PDF Datasheet ] | |
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