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74LS12 PDF даташит

Спецификация 74LS12 изготовлена ​​​​«Fairchild Semiconductor» и имеет функцию, называемую «Dual Retriggerable One-Shot with Clear and Complementary Outputs».

Детали детали

Номер произв 74LS12
Описание Dual Retriggerable One-Shot with Clear and Complementary Outputs
Производители Fairchild Semiconductor
логотип Fairchild Semiconductor логотип 

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74LS12 Даташит, Описание, Даташиты
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August 1986
Revised April 2000
DM74LS123
Dual Retriggerable One-Shot
with Clear and Complementary Outputs
General Description
The DM74LS123 is a dual retriggerable monostable multi-
vibrator capable of generating output pulses from a few
nano-seconds to extremely long duration up to 100% duty
cycle. Each device has three inputs permitting the choice of
either leading edge or trailing edge triggering. Pin (A) is an
active-LOW transition trigger input and pin (B) is an active-
HIGH transition trigger input. The clear (CLR) input termi-
nates the output pulse at a predetermined time indepen-
dent of the timing components. The clear input also serves
as a trigger input when it is pulsed with a low level pulse
transition ( ). To obtain the best trouble free operation
from this device please read the operating rules as well as
the Fairchild Semiconductor one-shot application notes
carefully and observe recommendations.
Features
s DC triggered from active-HIGH transition or active-LOW
transition inputs
s Retriggerable to 100% duty cycle
s Compensated for VCC and temperature variations
s Triggerable from CLEAR input
s DTL, TTL compatible
s Input clamp diodes
Ordering Code:
Order Number Package Number
Package Description
DM74LS123M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74LS123SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74LS123N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Inputs
CLEAR
A
LX
XH
XX
HL
H
L
H = HIGH Logic Level
L = LOW Logic Level
X = Can Be Either LOW or HIGH
↑ = Positive Going Transition
↓ = Negative Going Transition
= A Positive Pulse
= A Negative Pulse
B
X
X
L
H
H
Outputs
QQ
LH
LH
L H
© 2000 Fairchild Semiconductor Corporation DS006386
www.fairchildsemi.com









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74LS12 Даташит, Описание, Даташиты
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Functional Description
The basic output pulse width is determined by selection of
an external resistor (RX) and capacitor (CX). Once trig-
gered, the basic pulse width may be extended by retrigger-
ing the gated active-LOW transition or active-HIGH
transition inputs or be reduced by use of the active-LOW or
CLEAR input. Retriggering to 100% duty cycle is possible
by application of an input pulse train whose cycle time is
shorter than the output cycle time such that a continuous
HIGHlogic state is maintained at the Qoutput.
Operating Rules
1. An external resistor (RX) and an external capacitor (CX)
are required for proper operation. The value of CX may
vary from 0 to any necessary value. For small time con-
stants high-grade mica, glass, polypropylene, polycar-
bonate, or polystyrene material capacitors may be
used. For large time constants use tantalum or special
aluminum capacitors. If the timing capacitors have
leakages approaching 100 nA or if stray capacitance
from either terminal to ground is greater than 50 pF the
timing equations may not represent the pulse width the
device generates.
2. When an electrolytic capacitor is used for CX a switch-
ing diode is often required for standard TTL one-shots
to prevent high inverse leakage current. This switching
diode is not needed for the DM74LS123 one-shot and
should not be used. In general the use of the switching
diode is not recommended with retriggerable operation.
Furthermore, if a polarized timing capacitor is used on
the DM74LS123 the negative terminal of the capacitor
should be connected to the CEXTpin of the device
(Figure 1).
FIGURE 2.
5. For CX < 1000 pF see Figure 3 for tW vs. CX family
curves with RX as a parameter:
FIGURE 1.
3. For CX >> 1000 pF the output pulse width (tW) is
defined as follows:
tW = KRX CX
where [RX is in k]
[CX is in pF]
[tW is in ns]
K 0.37
4. The multiplicative factor K is plotted as a function of CX
below for design considerations:
FIGURE 3.
6. To obtain variable pulse widths by remote trimming, the
following circuit is recommended:
FIGURE 4.
“Rremote” should be as close to the device pin as possible.
7. The retriggerable pulse width is calculated as shown
below:
T = tW + tPLH = K × RX × CX + tPLH
The retriggered pulse width is equal to the pulse width
plus a delay time period (Figure 5).
www.fairchildsemi.com
FIGURE 5.
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74LS12 Даташит, Описание, Даташиты
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Operating Rules (Continued)
8. Output pulse width variation versus VCC and tempera-
tures: Figure 6 depicts the relationship between pulse
width variation versus VCC, and Figure 7 depicts pulse
width variation versus temperatures.
FIGURE 6.
9. Under any operating condition CX and RX must be kept
as close to the one-shot device pins as possible to min-
imize stray capacitance, to reduce noise pick-up, and
to reduce I-R and Ldi/dt voltage developed along their
connecting paths. If the lead length from CX to pins (6)
and (7) or pins (14) and (15) is greater than 3 cm, for
example, the output pulse width might be quite different
from values predicted from the appropriate equations.
A non-inductive and low capacitive path is necessary to
ensure complete discharge of CX in each cycle of its
operation so that the output pulse width will be accu-
rate.
10. The CEXT pins of this device are internally connected to
the internal ground. For optimum system performance
they should be hard wired to the systems return
ground plane.
11. VCC and ground wiring should conform to good high-
frequency standards and practices so that switching
transients on the VCC and ground return leads do not
cause interaction between one-shots. A 0.01 µF to 0.10
µF bypass capacitor (disk ceramic or monolithic type)
from VCC to ground is necessary on each device. Fur-
thermore, the bypass capacitor should be located as
close to the VCC-pin as space permits.
Note: For further detailed device characteristics and output per-
formance please refer to the Fairchild Semiconductor one-shot
application note AN-372.
FIGURE 7.
3 www.fairchildsemi.com










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