74LS174 PDF даташит
Спецификация 74LS174 изготовлена «ON Semiconductor» и имеет функцию, называемую «LOW POWER SCHOTTKY». |
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Детали детали
Номер произв | 74LS174 |
Описание | LOW POWER SCHOTTKY |
Производители | ON Semiconductor |
логотип |
8 Pages
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SN74LS174
Hex D Flip-Flop
The LSTTL / MSI SN74LS174 is a high speed Hex D Flip-Flop. The
device is used primarily as a 6-bit edge-triggered storage register. The
information on the D inputs is transferred to storage during the LOW
to HIGH clock transition. The device has a Master Reset to
simultaneously clear all flip-flops. The LS174 is fabricated with the
Schottky barrier diode process for high speed and is completely
compatible with all ON Semiconductor TTL families.
• Edge-Triggered D-Type Inputs
• Buffered-Positive Edge-Triggered Clock
• Asynchronous Common Reset
• Input Clamp Diodes Limit High Speed Termination Effects
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min Typ Max Unit
VCC Supply Voltage
TA Operating Ambient
Temperature Range
4.75 5.0 5.25
V
0 25 70 °C
IOH Output Current – High
IOL Output Current – Low
– 0.4
8.0
mA
mA
http://onsemi.com
LOW
POWER
SCHOTTKY
16
1
PLASTIC
N SUFFIX
CASE 648
16
1
SOIC
D SUFFIX
CASE 751B
ORDERING INFORMATION
Device
Package
Shipping
SN74LS174N 16 Pin DIP 2000 Units/Box
SN74LS174D
16 Pin
2500/Tape & Reel
© Semiconductor Components Industries, LLC, 1999
December, 1999 – Rev. 6
1
Publication Order Number:
SN74LS174/D
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SN74LS174
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC Q5 D5 D4 Q4 D3 Q3 CP
16 15 14 13 12 11 10 9
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
123
MR Q0 D0
4 56
D1 Q1 D2
78
Q2 GND
PIN NAMES
D0 – D5
CP
MR
Q0 – Q5
Data Inputs
Clock (Active HIGH Going Edge) Input
Master Reset (Active LOW) Input
Outputs
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.
LOADING (Note a)
HIGH
LOW
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 U.L.
LOGIC SYMBOL
3 4 6 11 13 14
D0 D1 D2 D3 D4 D5
9 CP
1 MR
Q0 Q1 Q2 Q3 Q4 Q5
2 5 7 10 12 15
VCC = PIN 16
GND = PIN 8
MR CP D5
1 9 14
LOGIC DIAGRAM
D4 D3 D2
13 11 6
D1
4
D0
3
DQ
CPCD
15
Q5
DQ
CPCD
DQ
CPCD
DQ
CPCD
12 10
Q4 Q3
VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
7
Q2
DQ
CPCD
5
Q1
DQ
CPCD
2
Q0
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SN74LS174
FUNCTIONAL DESCRIPTION
The LS174 consists of six edge-triggered D flip-flops with
individual D inputs and Q outputs. The Clock (CP) and
Master Reset (MR) are common to all flip-flops.
Each D input’s state is transferred to the corresponding
flip-flop’s output following the LOW to HIGH Clock (CP)
transition.
A LOW input to the Master Reset (MR) will force all
outputs LOW independent of Clock or Data inputs. The
LS174 is useful for applications where the true output only
is required and the Clock and Master Reset are common to
all storage elements.
TRUTH TABLE
Inputs (t = n, MR = H)
Outputs (t = n+1) Note 1
DQ
H
L
Note 1: t = n + 1 indicates conditions after next clock.
H
L
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
Parameter
Min Typ Max Unit
Test Conditions
VIH Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
VIL Input LOW Voltage
0.8
V
Guaranteed Input LOW Voltage for
All Inputs
VIK Input Clamp Diode Voltage
– 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA
VOH Output HIGH Voltage
2.7 3.5
V VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VOL Output LOW Voltage
0.25 0.4
0.35 0.5
V IOL = 4.0 mA
V IOL = 8.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
IIH Input HIGH Current
20 µA VCC = MAX, VIN = 2.7 V
0.1 mA VCC = MAX, VIN = 7.0 V
IIL Input LOW Current
– 0.4 mA VCC = MAX, VIN = 0.4 V
IOS
Short Circuit Current (Note 1)
– 20
– 100 mA VCC = MAX
ICC Power Supply Current
26 mA VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
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