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PDF 74LS174 Data sheet ( Hoja de datos )

Número de pieza 74LS174
Descripción HEX D FLIP-FLOP
Fabricantes Motorola Semiconductors 
Logotipo Motorola Semiconductors Logotipo

74LS174 datasheet


1. HEX D FLIP-FLOP - Motorola






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No Preview Available ! 74LS174 Hoja de datos, Descripción, Manual

HEX D FLIP-FLOP
The LSTTL / MSI SN54 / 74LS174 is a high speed Hex D Flip-Flop. The
device is used primarily as a 6-bit edge-triggered storage register. The
information on the D inputs is transferred to storage during the LOW to HIGH
clock transition. The device has a Master Reset to simultaneously clear all
flip-flops. The LS174 is fabricated with the Schottky barrier diode process for
high speed and is completely compatible with all Motorola TTL families.
Edge-Triggered D-Type Inputs
Buffered-Positive Edge-Triggered Clock
Asynchronous Common Reset
Input Clamp Diodes Limit High Speed Termination Effects
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC Q5 D5 D4 Q4 D3 Q3 CP
16 15 14 13 12 11 10 9
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
1 2 3 4 56 78
MR Q0 D0 D1 Q1 D2 Q2 GND
PIN NAMES
LOADING (Note a)
HIGH
LOW
D0 – D5
CP
MR
Q0 – Q5
Data Inputs
Clock (Active HIGH Going Edge) Input
Master Reset (Active LOW) Input
Outputs (Note b)
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
NOTES:
a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b. Temperature Ranges.
LOGIC DIAGRAM
MR CP D5 D4 D3
D2 D1
D0
1 9 14
13
11
6
43
DQ
CPCD
VCC = PIN 16
GND = PIN 8
15
Q5
= PIN NUMBERS
DQ
CPCD
DQ
CPCD
12 10
Q4 Q3
DQ
CPCD
7
Q2
DQ
CPCD
5
Q1
DQ
CPCD
2
Q0
SN54/74LS174
HEX D FLIP-FLOP
LOW POWER SCHOTTKY
16
1
J SUFFIX
CERAMIC
CASE 620-09
16
1
N SUFFIX
PLASTIC
CASE 648-08
16
1
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
LOGIC SYMBOL
3 4 6 11 13 14
D0 D1 D2 D3 D4 D5
9 CP
1 MR
Q0 Q1 Q2 Q3 Q4 Q5
2 5 7 10 12 15
VCC = PIN 16
GND = PIN 8
FAST AND LS TTL DATA
5-1

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