74LS175 PDF даташит
Спецификация 74LS175 изготовлена «ON Semiconductor» и имеет функцию, называемую «LOW POWER SCHOTTKY». |
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Детали детали
Номер произв | 74LS175 |
Описание | LOW POWER SCHOTTKY |
Производители | ON Semiconductor |
логотип |
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SN74LS175
Quad D Flip-Flop
The LSTTL / MSI SN74LS175 is a high speed Quad D Flip-Flop.
The device is useful for general flip-flop requirements where clock
and clear inputs are common. The information on the D inputs is
stored during the LOW to HIGH clock transition. Both true and
complemented outputs of each flip-flop are provided. A Master Reset
input resets all flip-flops, independent of the Clock or D inputs, when
LOW.
The LS175 is fabricated with the Schottky barrier diode process for
high speed and is completely compatible with all ON Semiconductor
TTL families.
• Edge-Triggered D-Type Inputs
• Buffered-Positive Edge-Triggered Clock
• Clock to Output Delays of 30 ns
• Asynchronous Common Reset
• True and Complement Output
• Input Clamp Diodes Limit High Speed Termination Effects
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min Typ Max Unit
VCC Supply Voltage
TA Operating Ambient
Temperature Range
4.75 5.0 5.25
V
0 25 70 °C
IOH Output Current – High
IOL Output Current – Low
– 0.4
8.0
mA
mA
http://onsemi.com
LOW
POWER
SCHOTTKY
16
1
PLASTIC
N SUFFIX
CASE 648
16
1
SOIC
D SUFFIX
CASE 751B
ORDERING INFORMATION
Device
Package
Shipping
SN74LS175N 16 Pin DIP 2000 Units/Box
SN74LS175D
16 Pin
2500/Tape & Reel
© Semiconductor Components Industries, LLC, 1999
December, 1999 – Rev. 6
1
Publication Order Number:
SN74LS175/D
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SN74LS175
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC Q3 Q3 D3 D2 Q2 Q2 CP
16 15 14 13 12 11 10 9
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
1 2 3 4 56 78
MR Q0 Q0 D0 D1 Q1 Q1 GND
PIN NAMES
D0 – D3
CP
MR
Q0 – Q3
Q0 – Q3
Data Inputs
Clock (Active HIGH Going Edge) Input
Master Reset (Active LOW) Input
True Outputs
Complemented Outputs
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.
LOADING (Note a)
HIGH
LOW
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 U.L.
5 U.L.
LOGIC SYMBOL
4 5 12 13
D0 D1 D2 D3
9 CP
1 MR
Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3
MR CP D3
1 9 13
3 2 6 7 11 10 14 15
VCC = PIN 16
GND = PIN 8
LOGIC DIAGRAM
D2 D1
12 5
D0
4
DQ
CP Q
CD
DQ
CP Q
CD
DQ
CP Q
CD
DQ
CP Q
CD
14 15
Q3 Q3
11 10
Q2 Q2
VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
67
Q1 Q1
32
Q0 Q0
http://onsemi.com
2
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SN74LS175
FUNCTIONAL DESCRIPTION
The LS175 consists of four edge-triggered D flip-flops
with individual D inputs and Q and Q outputs. The Clock and
Master Reset are common. The four flip-flops will store the
state of their individual D inputs on the LOW to HIGH Clock
(CP) transition, causing individual Q and Q outputs to
follow. A LOW input on the Master Reset (MR) will force
all Q outputs LOW and Q outputs HIGH independent of
Clock or Data inputs.
The LS175 is useful for general logic applications where
a common Master Reset and Clock are acceptable.
TRUTH TABLE
Inputs (t = n, MR = H)
Outputs (t = n+1) Note 1
D QQ
LL
HH
Note 1: t = n + 1 indicates conditions after next clock.
H
L
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
Parameter
Min Typ Max Unit
Test Conditions
VIH Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
VIL Input LOW Voltage
0.8
V
Guaranteed Input LOW Voltage for
All Inputs
VIK Input Clamp Diode Voltage
– 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA
VOH Output HIGH Voltage
2.7 3.5
V VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VOL Output LOW Voltage
0.25 0.4
0.35 0.5
V IOL = 4.0 mA
V IOL = 8.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
IIH Input HIGH Current
20 µA VCC = MAX, VIN = 2.7 V
0.1 mA VCC = MAX, VIN = 7.0 V
IIL Input LOW Current
– 0.4 mA VCC = MAX, VIN = 0.4 V
IOS
Short Circuit Current (Note 1)
– 20
– 100 mA VCC = MAX
ICC Power Supply Current
18 mA VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
http://onsemi.com
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