PDF 74LS195 Data sheet ( Hoja de datos )

Número de pieza	74LS195
Descripción	LOW POWER SCHOTTKY
Fabricantes	ON Semiconductor
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No Preview Available ! SN74LS195A Universal 4-Bit Shift Register The SN74LS195A is a high speed 4-Bit Shift Register offering typical shift frequencies of 39 MHz. It is useful for a wide variety of register and counting applications. It utilizes the Schottky diode clamped process to achieve high speeds and is fully compatible with all ON Semiconductor TTL products. • Typical Shift Right Frequency of 39 MHz • Asynchronous Master Reset • J, K Inputs to First Stage • Fully Synchronous Serial or Parallel Data Transfers • Input Clamp Diodes Limit High Speed Termination Effects GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage TA Operating Ambient Temperature Range 4.75 5.0 5.25 V 0 25 70 °C IOH Output Current – High IOL Output Current – Low – 0.4 8.0 mA mA http://onsemi.com LOW POWER SCHOTTKY 16 1 PLASTIC N SUFFIX CASE 648 16 1 SOIC D SUFFIX CASE 751B ORDERING INFORMATION Device Package Shipping SN74LS195AN 16 Pin DIP 2000 Units/Box SN74LS195AD 16 Pin 2500/Tape & Reel © Semiconductor Components Industries, LLC, 1999 December, 1999 – Rev. 6 1 Publication Order Number: SN74LS195A/D 1 page SN74LS195A DEFINITIONS OF TERMS SETUP TIME(ts) —is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW to HIGH in order to be recognized and transferred to the outputs. HOLD TIME (th) — is defined as the minimum time following the clock transition from LOW to HIGH that the logic level must be maintained at the input in order to ensure continued recognition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW to HIGH and still be recognized. RECOVERY TIME (trec) — is defined as the minimum time required between the end of the reset pulse and the clock transition from LOW to HIGH in order to recognize and transfer HIGH Data to the Q outputs. AC WAVEFORMS The shaded areas indicate when the input is permitted to change for predictable output performance. tW CLOCK tPHL OUTPUT 1.3 V 1.3 V 1.3 V tPLH 1.3 V CONDITIONS: J = PE = MR = H K=L Figure 1. Clock to Output Delays and Clock Pulse Width PE J&K ts(L) th(L) = 0 P0 P1 P2 P3 th(L) = 0 ts(L) ts(H) th(H) = 0 CLOCK 1.3 V OUTPUT* 1.3 V ts(H) th(H) = 0 1.3 V CONDITIONS: MR = H J AND K SET–UP TIME AFFECTS Q0 ONLY Figure 3. Setup (ts) and Hold (th) Time for Serial Data (J & K) and Parallel Data (P0, P1, P2, P3) MR tW 1.3 V 1.3 V CLOCK OUTPUT trec 1.3 V tPHL 1.3 V CONDITIONS: PE = L PO = P1 = P2 = P3 = H Figure 2. Master Reset Pulse Width, Master Reset to Output Delay and Master Reset to Clock Recovery Time LOAD PARALLEL DATA LOAD SERIAL DATA SHIFT RIGHT PE CLOCK 1.3 V ts(L) trel 1.3 V ts(H) trel 1.3 V 1.3 V OUTPUT Qn = Pn Qn = Qn–1 CONDITIONS: MR = H *Q0 STATE WILL BE DETERMINED BY J AND K INPUTS. Figure 4. Setup (ts) and Hold (th) Time for PE Input http://onsemi.com 5 5 Page

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