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74LS273 PDF даташит

Спецификация 74LS273 изготовлена ​​​​«Motorola Semiconductors» и имеет функцию, называемую «OCTAL D FLIP-FLOP WITH CLEAR».

Детали детали

Номер произв 74LS273
Описание OCTAL D FLIP-FLOP WITH CLEAR
Производители Motorola Semiconductors
логотип Motorola Semiconductors логотип 

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74LS273 Даташит, Описание, Даташиты
OCTAL D FLIP-FLOP WITH CLEAR
The SN54 / 74LS273 is a high-speed 8-Bit Register. The register consists of
eight D-Type Flip-Flops with a Common Clock and an asynchronous active
LOW Master Reset. This device is supplied in a 20-pin package featuring 0.3
inch lead spacing.
8-Bit High Speed Register
Parallel Register
Common Clock and Master Reset
Input Clamp Diodes Limit High-Speed Termination Effects
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 CP
20 19 18 17 16 15 14 13 12 11
SN54/74LS273
OCTAL D FLIP-FLOP
WITH CLEAR
LOW POWER SCHOTTKY
20
1
J SUFFIX
CERAMIC
CASE 732-03
1 2 3 4 5 6 7 8 9 10
MR Q0 D0 D1 Q1 Q2 D2 D3 Q3 GND
PIN NAMES
LOADING (Note a)
HIGH
LOW
CP
Clock (Active HIGH Going Edge) Input
0.5 U.L.
0.25 U.L.
D0 – D7
MR
Data Inputs
Master Reset (Active LOW) Input
0.5 U.L.
0.5 U.L.
0.25 U.L.
0.25 U.L.
Q0 – Q7 Register Outputs (Note b)
10 U.L. 5 (2.5) U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial
(74) Temperature Ranges.
TRUTH TABLE
MR CP Dx Qx
LXX
HH
HL
L
H
L
H = HIGH Logic Level
L = LOW Logic Level
X = Immaterial
LOGIC DIAGRAM
3
4
7
8
13
11 D0 D1 D2 D3 D4
CP
20
1
20
1
N SUFFIX
PLASTIC
CASE 738-03
DW SUFFIX
SOIC
CASE 751D-03
ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXDW SOIC
14 17 18
D5 D6 D7
CP D
CP D
CP D
CP D
CP D
CP D
CP D
CP D
1
CD Q
CD Q
CD Q
CD Q
CD Q
CD Q
CD Q
CD Q
MR
VCC = PIN 20
GND = PIN 10
= PIN NUMBERS
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
12
15 16
19
FAST AND LS TTL DATA
5-447









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74LS273 Даташит, Описание, Даташиты
SN54 / 74LS273
FUNCTIONAL DESCRIPTION
The SN54 / 74LS273 is an 8-Bit Parallel Register with a
common Clock and common Master Reset.
When the MR input is LOW, the Q outputs are LOW,
independent of the other inputs. Information meeting the setup
and hold time requirements of the D inputs is transferred to the
Q outputs on the LOW-to-HIGH transition of the clock input.
GUARANTEED OPERATING RANGES
Symbol
Parameter
VCC
Supply Voltage
TA Operating Ambient Temperature Range
IOH Output Current — High
IOL Output Current — Low
Min Typ Max Unit
54 4.5 5.0 5.5
74 4.75 5.0 5.25
V
54 – 55 25 125 °C
74 0 25 70
54, 74
– 0.4
mA
54 4.0 mA
74 8.0
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
Parameter
Min Typ Max Unit
Test Conditions
VIH Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
54
VIL Input LOW Voltage
74
0.7 Guaranteed Input LOW Voltage for
0.8 V All Inputs
VIK
VOH
Input Clamp Diode Voltage
Output HIGH Voltage
54
74
– 0.65 – 1.5
2.5 3.5
2.7 3.5
V VCC = MIN, IIN = – 18 mA
V VCC = MIN, IOH = MAX, VIN = VIH
V or VIL per Truth Table
VOL
Output LOW Voltage
54, 74
74
0.25 0.4
0.35 0.5
V IOL = 4.0 mA VCC = VCC MIN,
VIN = VIL or VIH
V IOL = 8.0 mA per Truth Table
IIH Input HIGH Current
20 µA VCC = MAX, VIN = 2.7 V
0.1 mA VCC = MAX, VIN = 7.0 V
IIL Input LOW Current
– 0.4 mA VCC = MAX, VIN = 0.4 V
IOS
Short Circuit Current (Note 1)
– 20
– 100 mA VCC = MAX
ICC Power Supply Current
27
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
mA VCC = MAX
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Limits
Symbol
Parameter
Min Typ Max
fMAX
Maximum Input Clock Frequency
30 40
tPHL
Propagation Delay, MR to Q Output
18 27
tPLH
tPHL
Propagation Delay, Clock to Output
17 27
18 27
Unit
MHz
ns
ns
Test Conditions
Figure 1
Figure 2
Figure 1
FAST AND LS TTL DATA
5-448









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74LS273 Даташит, Описание, Даташиты
SN54 / 74LS273
AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V)
Symbol
tw
ts
th
trec
Parameter
Pulse Width, Clock or Clear
Data Setup Time
Hold Time
Recovery Time
Min
20
20
5.0
25
Limits
Typ
Max
Unit
ns
ns
ns
ns
Test Conditions
Figure 1
Figure 1
Figure 1
Figure 2
AC WAVEFORMS
CP
D
Qn
1.3 V
1.3 V
1/f max
tW
1.3 V
1.3 V
ts(H)
* 1.3 V
th(H)
ts(L)
tPLH
1.3 V
1.3 V
th(L)
1.3 V
tPHL
1.3 V
tPHL
tPLH
*The shaded areas indicate when the input is permitted to
*change for predictable output performance.
Figure 1. Clock to Output Delays, Clock Pulse Width,
Frequency, Setup and Hold Times Data to Clock
MR
tW
1.3 V
CP
Qn
tPLH
Qn
tPHL
1.3 V
1.3 V
trec
1.3 V
1.3 V
1.3 V
Figure 2. Master Reset to Output Delay, Master Reset
Pulse Width, and Master Reset Recovery Time
DEFINITION OF TERMS
SETUP TIME (ts) — is defined as the minimum time required
for the correct logic level to be present at the logic input prior to
the clock transition from LOW-to-HIGH in order to be recog-
nized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time following
the clock transition from LOW-to-HIGH that the logic level
must be maintained at the input in order to ensure continued
recognition. A negative HOLD TIME indicates that the correct
logic level may be released prior to the clock transition from
LOW-to-HIGH and still be recognized.
RECOVERY TIME (trec) — is defined as the minimum time
required between the end of the reset pulse and the clock
transition from LOW-to-HIGH in order to recognize and
transfer HIGH data to the Q outputs.
FAST AND LS TTL DATA
5-449










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