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74LS298 PDF даташит

Спецификация 74LS298 изготовлена ​​​​«ON Semiconductor» и имеет функцию, называемую «LOW POWER SCHOTTKY».

Детали детали

Номер произв 74LS298
Описание LOW POWER SCHOTTKY
Производители ON Semiconductor
логотип ON Semiconductor логотип 

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74LS298 Даташит, Описание, Даташиты
SN74LS298
Quad 2-Input Multiplexer
with Storage
The SN74LS298 is a Quad 2-Port Register. It is the logical
equivalent of a quad 2-input multiplexer followed by a quad 4-bit
edge-triggered register. A Common Select input selects between two
4-bit input ports (data sources.) The selected data is transferred to the
output register synchronous with the HIGH to LOW transition of the
Clock input.
The LS298 is fabricated with the Schottky barrier process for high
speed and is completely compatible with all ON Semiconductor TTL
families.
Select From Two Data Sources
Fully Edge-Triggered Operation
Typical Power Dissipation of 65 mW
Input Clamp Diodes Limit High Speed Termination Effects
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min Typ Max Unit
VCC Supply Voltage
TA Operating Ambient
Temperature Range
4.75 5.0 5.25
V
0 25 70 °C
IOH Output Current – High
IOL Output Current – Low
– 0.4
8.0
mA
mA
http://onsemi.com
LOW
POWER
SCHOTTKY
16
1
PLASTIC
N SUFFIX
CASE 648
16
1
SOIC
D SUFFIX
CASE 751B
ORDERING INFORMATION
Device
Package
Shipping
SN74LS298N 16 Pin DIP 2000 Units/Box
SN74LS298D
16 Pin
2500/Tape & Reel
© Semiconductor Components Industries, LLC, 1999
December, 1999 – Rev. 6
1
Publication Order Number:
SN74LS298/D









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74LS298 Даташит, Описание, Даташиты
SN74LS298
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC Qa Qb Qc Qd CP S
16 15 14 13 12 11 10
I0c
9
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
1 2 3 4 56 78
I1b I1a I0a I0b I1c I1d I0d GND
PIN NAMES
S
CP
I0a – I0d
I1a – I1d
Qa – Qd
Common Select Input
Clock (Active LOW Going Edge) Input
Data Inputs from Source 0
Data Inputs from Source 1
Register Outputs
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.
LOADING (Note a)
HIGH
LOW
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 U.L.
LOGIC SYMBOL
3 2 4 1 9 5 76
I0a I1a I0b I1b I0c I1c I0d I1d
10 S
11 CP
Qa Qb Qc
Qd
15 14 13
VCC = PIN 16
GND = PIN 8
12
http://onsemi.com
2









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74LS298 Даташит, Описание, Даташиты
SN74LS298
LOGIC OR BLOCK DIAGRAM
I1a I0a
I1b I0b
23 1 4
S
10
I1c
5
I0c
9
I1d
6
I0d
7
CP
11
VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
R
CP
S Qa
15
Qa
R
CP
S Qb
14
Qb
R
CP
S Qc
13
Qc
R
CP
S Qd
12
Qd
FUNCTIONAL DESCRIPTION
The LS298 is a high speed Quad 2-Port Register. It selects
four bits of data from two sources (ports)under the control
of a Common Select Input (S). The selected data is
transferred to the 4-bit output register synchronous with the
HIGH to LOW transition of the Clock input (CP). The 4-bit
output register is fully edge-triggered. The Data inputs (I)
and Select input (S) must be stable only one setup time prior
to the HIGH to LOW transition of the clock for predictable
operation.
TRUTH TABLE
INPUTS
OUTPUT
S I0 I1
Q
I IX
I hX
h XI
h Xh
L
H
L
H
L = LOW Voltage Level
H = HIGH Voltage Level
X = Don’t Care
I = LOW Voltage Level one setup time prior to the HIGH to LOW clock transition.
h = HIGH Voltage Level one setup time prior to the HIGH to LOW clock transition.
http://onsemi.com
3










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