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Número de pieza | 74LS73 | |
Descripción | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs | |
Fabricantes | Fairchild Semiconductor | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de 74LS73 (archivo pdf) en la parte inferior de esta página. Total 5 Páginas | ||
No Preview Available ! August 1986
Revised March 2000
DM74LS73A
Dual Negative-Edge-Triggered Master-Slave
J-K Flip-Flops with Clear and Complementary Outputs
General Description
This device contains two independent negative-edge-trig-
gered J-K flip-flops with complementary outputs. The J and
K data is processed by the flip-flops on the falling edge of
the clock pulse. The clock triggering occurs at a voltage
level and is not directly related to the transition time of the
negative going edge of the clock pulse. The data on the J
and K inputs is allowed to change while the clock is HIGH
or LOW without affecting the outputs as long as setup and
hold times are not violated. A low logic level on the clear
input will reset the outputs regardless of the levels of the
other inputs.
Ordering Code:
Order Number Package Number
Package Description
DM74LS73AM
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
DM74LS73AN
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Inputs
Outputs
CLR CLK
J
K
Q
Q
L X XX L
H
H
↓
LL
Q0
Q0
H ↓ HL H
L
H ↓ LH L
H
H ↓ HH
Toggle
H
H
XX
Q0
Q0
H = HIGH Logic Level
L = LOW Logic Level
X = Either LOW or HIGH Logic Level
↓ = Negative going edge of pulse.
Q0 = The output logic level before the indicated input conditions were
established.
Toggle = Each output changes to the complement of its previous level on
each falling edge of the clock pulse.
© 2000 Fairchild Semiconductor Corporation DS006372
www.fairchildsemi.com
1 page Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
5 www.fairchildsemi.com
5 Page |
Páginas | Total 5 Páginas | |
PDF Descargar | [ Datasheet 74LS73.PDF ] |
Número de pieza | Descripción | Fabricantes |
74LS73 | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs | Fairchild Semiconductor |
74LS73 | Dual J-K Flip-Flops(with Clear) | Hitachi Semiconductor |
74LS73 | DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP | Motorola Semiconductors |
74LS73A | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs | Fairchild Semiconductor |
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