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Спецификация 74LS73A изготовлена «Fairchild Semiconductor» и имеет функцию, называемую «Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs». |
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Детали детали
Номер произв | 74LS73A |
Описание | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs |
Производители | Fairchild Semiconductor |
логотип |
5 Pages
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August 1986
Revised March 2000
DM74LS73A
Dual Negative-Edge-Triggered Master-Slave
J-K Flip-Flops with Clear and Complementary Outputs
General Description
This device contains two independent negative-edge-trig-
gered J-K flip-flops with complementary outputs. The J and
K data is processed by the flip-flops on the falling edge of
the clock pulse. The clock triggering occurs at a voltage
level and is not directly related to the transition time of the
negative going edge of the clock pulse. The data on the J
and K inputs is allowed to change while the clock is HIGH
or LOW without affecting the outputs as long as setup and
hold times are not violated. A low logic level on the clear
input will reset the outputs regardless of the levels of the
other inputs.
Ordering Code:
Order Number Package Number
Package Description
DM74LS73AM
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
DM74LS73AN
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Inputs
Outputs
CLR CLK
J
K
Q
Q
L X XX L
H
H
↓
LL
Q0
Q0
H ↓ HL H
L
H ↓ LH L
H
H ↓ HH
Toggle
H
H
XX
Q0
Q0
H = HIGH Logic Level
L = LOW Logic Level
X = Either LOW or HIGH Logic Level
↓ = Negative going edge of pulse.
Q0 = The output logic level before the indicated input conditions were
established.
Toggle = Each output changes to the complement of its previous level on
each falling edge of the clock pulse.
© 2000 Fairchild Semiconductor Corporation DS006372
www.fairchildsemi.com
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Absolute Maximum Ratings(Note 1)
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
0°C to +70°C
Storage Temperature Range
−65°C to +150°C
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Recommended Operating Conditions
Symbol
Parameter
Min
VCC Supply Voltage
4.75
VIH HIGH Level Input Voltage
2
VIL LOW Level Input Voltage
IOH HIGH Level Output Current
IOL LOW Level Output Current
fCLK Clock Frequency (Note 2)
0
fCLK Clock Frequency (Note 3)
0
tW
Pulse Width
Clock HIGH
20
(Note 2)
Preset LOW
25
Clear LOW
25
tW
Pulse Width
Clock HIGH
25
(Note 3)
Preset LOW
30
Clear LOW
30
tSU Setup Time (Note 2)(Note 4)
20↓
tSU Setup Time (Note 3)(Note 4)
25↓
tH Hold Time (Note 2)(Note 4)
0↓
tH Hold Time (Note 3)(Note 4)
5↓
TA Free Air Operating Temperature
0
Note 2: CL = 15 pF, RL = 2 kΩ, TA = 25°C and VCC = 5V.
Note 3: CL = 50 pF, RL = 2 kΩ, TA = 25°C and VCC = 5V.
Note 4: The symbol (↓) indicates the falling edge of the clock pulse is used for reference.
Nom
5
Max
5.25
0.8
−0.4
8
30
25
70
Units
V
V
V
mA
mA
MHz
MHz
ns
ns
ns
ns
ns
ns
°C
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Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Typ
Min Max
(Note 5)
Units
VI Input Clamp Voltage
VOH HIGH Level
Output Voltage
VOL LOW Level
Output Voltage
II Input Current @ Max
Input Voltage
VCC = Min, II = −18 mA
VCC = Min, IOH = Max
VIL = Max, VIH = Min
VCC = Min, IOL = Max
VIL = Max, VIH = Min
IOL = 4 mA, VCC = Min
VCC = Max
VI = 7V
J, K
Clear
Clock
−1.5 V
2.7 3.4
V
0.35
0.25
0.5
0.4
0.1
0.3
0.4
V
mA
IIH HIGH Level
Input Current
VCC = Max
VI = 2.7V
J, K
Clear
Clock
20
60 µA
80
IIL LOW Level
Input Current
VCC = Max
VI = 0.4V
J, K
Clear
Clock
−0.4
−0.8 mA
−0.8
IOS Short Circuit Output Current
ICC Supply Current
Note 5: All typicals are at VCC = 5V, TA = 25°C.
VCC = Max (Note 6)
VCC = Max (Note 7)
−20
−100
mA
4 6 mA
Note 6: Not more than one output should be shorted at a time, and the duration should not exceed one second. For devices, with feedback from the outputs,
where shorting the outputs to ground may cause the outputs to change logic state, an equivalent test may be performed where VO = 2.125V with the mini-
mum and maximum limits reduced by one half from their stated values. This is very useful when using automatic test equipment.
Note 7: With all outputs OPEN, ICC is measured with the Q and Q outputs HIGH in turn. At the time of measurement, the clock is grounded.
Switching Characteristics
at VCC = 5V and TA = 25°C
Symbol
Parameter
From (Input)
To (Output)
fMAX
tPHL
tPLH
tPLH
tPHL
Maximum Clock Frequency
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Clear
to Q
Clear
to Q
Clock to
Q or Q
Clock to
Q or Q
RL = 2 kΩ
CL = 15 pF
CL = 50 pF
Min Max Min Max
30 25
20 28
20 24
20 24
20 28
Units
MHz
ns
ns
ns
ns
3 www.fairchildsemi.com
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