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74LV164 PDF даташит

Спецификация 74LV164 изготовлена ​​​​«Philips» и имеет функцию, называемую «8-bit serial-in/parallel-out shift register».

Детали детали

Номер произв 74LV164
Описание 8-bit serial-in/parallel-out shift register
Производители Philips
логотип Philips логотип 

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74LV164 Даташит, Описание, Даташиты
INTEGRATED CIRCUITS
74LV164
8-bit serial-in/parallel-out shift register
Product specification
Supersedes data of 1997 Mar 28
IC24 Data Handbook
1998 May 07
Philips
Semiconductors









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74LV164 Даташит, Описание, Даташиты
Philips Semiconductors
8-bit serial-in/parallel-out shift register
Product specification
74LV164
FEATURES
Wide operating voltage: 1.0 to 5.5V
Optimized for Low Voltage applications: 1.0 to 3.6V
Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V
Typical VOLP (output ground bounce) t 0.8V @ VCC = 3.3V,
Tamb = 25°C
Typical VOHV (output VOH undershoot) u 2V @ VCC = 3.3V,
Tamb = 25°C
Gated serial data inputs
Asynchronous master reset
Output capability: standard
ICC category: MSI
DESCRIPTION
The 74LV164 is a low-voltage Si-gate CMOS device and is pin and
function compatible with the 74HC/HCT164.
The 74LV164 is an 8-bit edge-triggered shift register with serial data
entry and an output from each of the eight stages. Data is entered
serially through one of two inputs (Dsa or Dsb); either input can be
used as an active HIGH enable for data entry through the other
input. Both inputs must be connected together or an unused input
must be tied HIGH.
Data shifts one place to the right on each LOW-to-HIGH transition of
the clock (CP) input and enters into Q0, which is the logical AND of
the two data inputs (Dsa, Dsb) that existed one set-up time prior to
the rising clock edge.
A LOW on the master reset (MR) input overrides all other inputs and
clears the register asynchronously, forcing all outputs LOW.
QUICK REFERENCE DATA
GND = 0V; Tamb = 25°C; tr =tf v2.5 ns
SYMBOL
PARAMETER
CONDITIONS
tPHL/tPLH
fmax
CI
CPD
Propagation delay
CP to Qn
MR to Qn
Maximum clock frequency
Input capacitance
Power dissipation capacitance per gate
CL = 15pF
VCC = 3.3V
VCC = 3.3V
Notes 1 and 2
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD VCC2 x fi )S (CL VCC2 fo) where:
fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
S (CL VCC2 fo) = sum of the outputs.
2. The condition is VI = GND to VCC
TYPICAL
12
12
78
3.5
40
ORDERING INFORMATION
PACKAGES
14-Pin Plastic DIL
14-Pin Plastic SO
14-Pin Plastic SSOP Type II
14-Pin Plastic TSSOP Type I
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
–40°C to +125°C
74LV164 N
–40°C to +125°C
74LV164 D
–40°C to +125°C
74LV164 DB
–40°C to +125°C
74LV164 PW
NORTH AMERICA
74LV164 N
74LV164 D
74LV164 DB
74LV164PW DH
UNIT
ns
MHz
pF
pF
PKG. DWG. #
SOT27-1
SOT108-1
SOT337-1
SOT402-1
1998 May 07
2 853–1961 19349









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74LV164 Даташит, Описание, Даташиты
Philips Semiconductors
8-bit serial-in/parallel-out shift register
Product specification
74LV164
PIN CONFIGURATION
Dsa 1
Dsb 2
Q0 3
Q1 4
Q2 5
Q3 6
GND 7
LOGIC SYMBOL
14 VCC
13 Q7
12 Q6
11 Q5
10 Q4
9 MR
8 CP
SV00381
1
Dsa
Dsb
2
Q0 3
Q1 4
Q2 5
Q3 6
Q4 10
8 CP
Q5 11
Q6 12
9 MR
Q7 13
SV00382
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
1,2
3, 4, 5, 6,
10, 11,
12, 13
Dsa, Dsb
Q0 to Q7
7 GND
8 CP
9 MR
14 VCC
FUNCTION
Data inputs
Outputs
Ground (0V)
Clock input (LOW-to-HIGH, edge-trig-
gered)
Master reset input (active LOW)
Positive supply voltage
LOGIC SYMBOL (IEEE/IEC)
SRG8
8 C1/
9
R
1&
2 1D
3
4
5
6
10
11
12
13
SV00383
1998 May 07
3










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