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74LV595 PDF даташит

Спецификация 74LV595 изготовлена ​​​​«Philips» и имеет функцию, называемую «8-bit serial-in/serial or parallel-out shift register with output latches 3-State».

Детали детали

Номер произв 74LV595
Описание 8-bit serial-in/serial or parallel-out shift register with output latches 3-State
Производители Philips
логотип Philips логотип 

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74LV595 Даташит, Описание, Даташиты
INTEGRATED CIRCUITS
74LV595
8-bit serial-in/serial or parallel-out shift
register with output latches (3-State)
Product specification
IC24 Data Handbook
1998 Apr 20
Philips
Semiconductors









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74LV595 Даташит, Описание, Даташиты
Philips Semiconductors
8-bit serial-in/serial or parallel-out shift register
with output latches (3-State)
Product specification
74LV595
FEATURES
Optimized for Low Voltage applications: 1.0V to 3.6V
Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V
Typical VOLP (output ground bounce) < 0.8V at VCC = 3.3V,
Tamb = 25°C
Typical VOHV (output VOH undershoot) > 2V at VCC = 3.3V,
Tamb = 25°C
8-bit serial input
8-bit serial or parallel output
Storage register with 3-State outputs
Shift register with direct clear
Output capability:
– parallel outputs; bus driver
– serial output; standard
ICC category: MSI
QUICK REFERENCE DATA
GND = 0V; Tamb = 25°C; tr =tf v2.5 ns
SYMBOL
PARAMETER
APPLICATIONS
Serial-to-parallel data conversion
Remote control holding register
DESCRIPTION
The 74LV595 is a low-voltage Si-gate CMOS device that is pin and
function compatible with 74HC/HCT595.
The74LV595 is an 8-stage serial shift register with a storage register
and 3-State outputs. The shift register and storage register have
separate clocks.
Data is shifted on the positive-going transitions of the SHCP input.
The data in each register is transferred to the storage register on a
positive-going transition of the STCP input. If both clocks are
connected together, the shift register will always be one clock pulse
ahead of the storage register.
The shift register has a serial input (DS) and a serial standard output
(Q7’) all for cascading. It is also provided with asynchronous reset
(active LOW) for all 8 shift register stages. The storage register has
8 parallel 3-State bus driver outputs. Data in the storage register
appears at the output whenever the output enable input (OE) is
LOW.
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
fmax
CI
CPD
Propagation delay
SHCP to Q7’
STCP to Q7’
MR to Q7’
Maximum clock frequency SHCP, STCP
Input capacitance
Power dissipation capacitance per gate
CL = 15pF
VCC= 3.3V
VCC = 3.3V
Notes 1 and 2
15
16
ns
14
77 MHz
3.5 pF
115 pF
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD VCC2 x fi (CL VCC2 fo) where:
fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
ȍ (CL VCC2 fo) = sum of the outputs.
2. The condition is VI = GND to VCC.
ORDERING AND PACKAGE INFORMATION
PACKAGES
TEMPERATURE RANGE
16-Pin Plastic DIL
–40°C to +125°C
16-Pin Plastic SO
–40°C to +125°C
16-Pin Plastic SSOP Type II
–40°C to +125°C
16-Pin Plastic TSSOP Type I
–40°C to +125°C
OUTSIDE NORTH AMERICA
74LV595 N
74LV595 D
74LV595 DB
74LV595 PW
NORTH AMERICA
74LV595 N
74LV595 D
74LV595 DB
74LV595PW DH
PKG. DWG. #
SOT38-4
SOT109-1
SOT338-1
SOT403-1
1998 Apr 20
2 853-1987 19255









No Preview Available !

74LV595 Даташит, Описание, Даташиты
Philips Semiconductors
8-bit serial-in/serial or parallel-out shift register
with output latches (3-State)
Product specification
74LV595
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
FUNCTION
15, 1, 2, 3,
4, 5, 6, 7
Q0 to Q7 Parallel data output
8 GND Ground (0V)
9 Q7’ Serial data output
10 MR Master reset (active LOW)
11 SHCP Shift register clock input
12 STCP Storage register clock input
13 OE Output enable input (active LOW)
14 DS Serial data input
16 VCC Positive supply voltage
FUNCTION TABLE
INPUTS
SHCP
X
STCP
X
OE
L
X°L
XXH
MR
L
L
L
°XLH
DS
X
X
X
H
X ° LHX
° ° LH
H = HIGH voltage level
L = LOW voltage level
X = Don’t care
Z = High impedance OFF-state
NC= No change
° = LOW-to-HIGH clock transition
= HIGH-to-LOW transition
X
OUTPUTS
Q7’ Qn
L NC
LL
LZ
Q6’ NC
NC Qn’
Q6’ Qn’
PIN CONFIGURATION
Q1 1
Q2 2
Q3 3
Q4 4
Q5 5
Q6 6
Q7 7
GND 8
16 VCC
15 Q0
14 DS
13 OE
12 STCP
11 SHCP
10 MR
9 Q7’
SV00720
FUNCTION
A LOW level on MR only affects the shift registers
Empty shift register loaded into storage register
Shift register clear. Parallel outputs in high-impedance OFF-states
Logic high level shifted into shift register stage 0. Contents of all shift
register stages shifted through, e.g. previous state of stage 6 (internal
Q6’) appears on the serial output (Q7’)
Contents of shift register stages (internal Qn’) are transferred to the
storage register and parallel output stages
Contents of shift register shifted through. Previous contents of the shift
register are transferred to the storage register and the parallel output
stages
1998 Apr 20
3










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Номер в каталогеОписаниеПроизводители
74LV5958-bit serial-in/serial or parallel-out shift register with output latches 3-StatePhilips
Philips

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