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74LV74 PDF даташит

Спецификация 74LV74 изготовлена ​​​​«Philips» и имеет функцию, называемую «Dual D-type flip-flop with set and reset; positive-edge trigger».

Детали детали

Номер произв 74LV74
Описание Dual D-type flip-flop with set and reset; positive-edge trigger
Производители Philips
логотип Philips логотип 

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74LV74 Даташит, Описание, Даташиты
INTEGRATED CIRCUITS
74LV74
Dual D-type flip-flop with set and reset;
positive-edge trigger
Product specification
Supersedes data of 1996 Nov 07
IC24 Data Handbook
1998 Apr 20
Philips
Semiconductors









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74LV74 Даташит, Описание, Даташиты
Philips Semiconductors
Dual D-type flip-flop with set and reset;
positive edge-trigger
Product specification
74LV74
FEATURES
Wide operating voltage: 1.0 to 5.5V
Optimized for Low Voltage applications: 1.0 to 3.6V
Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V
Typical VOLP (output ground bounce) t 0.8V @ VCC = 3.3V,
Tamb = 25°C
Typical VOHV (output VOH undershoot) u 2V @ VCC = 3.3V,
Tamb = 25°C
Output capability: standard
ICC category: flip-flops
DESCRIPTION
The 74LV74 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT74.
The 74LV74 is a dual positive edge triggered, D-type flip-flop with
individual data (D) inputs, clock (CP) inputs, set (SD) and (RD)
inputs; also complementary Q and Q outputs.
The set and reset are asynchronous active LOW inputs and operate
independently of the clock input. Information on the data input is
transferred to the Q output on the LOW-to-HIGH transition of the
clock pulse. The D inputs must be stable one set-up time prior to the
LOW-to-HIGH clock transition, for predictable operation.
Schmitt-trigger action in the clock input makes the circuit highly
tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0V; Tamb = 25°C; tr =tf v2.5 ns
SYMBOL
PARAMETER
CONDITIONS
tPHL/tPLH
Propagation delay
nCP to nQ, nQ
nSD to nQ, nQ
nRD to nQ, nQ
CL = 15pF
VCC = 3.3V
fmax Maximum clock frequency
CL = 15pF
VCC = 3.3V
CI Input capacitance
CPD Power dissipation capacitance per flip-flop Notes 1 and 2
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD VCC2 x fi )S (CL VCC2 fo) where:
fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
S (CL VCC2 fo) = sum of the outputs.
2. The condition is VI = GND to VCC
TYPICAL
11
14
14
76
3.5
24
UNIT
ns
MHz
pF
pF
ORDERING INFORMATION
PACKAGES
14-Pin Plastic DIL
14-Pin Plastic SO
14-Pin Plastic SSOP Type II
14-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
OUTSIDE NORTH AMERICA
74LV74 N
74LV74 D
74LV74 DB
74LV74 PW
NORTH AMERICA
74LV74 N
74LV74 D
74LV74 DB
74LV74PW DH
PKG. DWG. #
SOT27-1
SOT108-1
SOT337-1
SOT402-1
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
1, 13
2, 12
1RD, 2RD
1D, 2D
3, 11
1CP, 2CP
4, 10
5, 9
6, 8
7
14
1SD, 2SD
1Q, 2Q
1Q, 2Q
GND
VCC
FUNCTION
Asynchronous reset-direct input
(active-LOW)
Data inputs
Clock input (LOW-to-HIGH),
edge-triggered)
Asynchronous set-direct input
(active-LOW)
True flip-flop outputs
Complement flip-flop outputs
Ground (0V)
Positive supply voltage
FUNCTION TABLE
INPUTS
SD RD CP
L HX
H LX
L LX
D
X
X
X
OUTPUTS
QQ
HL
LH
HH
INPUTS
OUTPUTS
SD
RD
CP
D
Qn+1
Qn+1
H H°L L H
H H °HH L
H = HIGH voltage level
L = LOW voltage level
X = don’t care
° = LOW-to-HIGH CP transition
Qn+1 = state after the next LOW-to-HIGH CP transition
1998 Apr 20
2 853-1888 19258









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74LV74 Даташит, Описание, Даташиты
Philips Semiconductors
Dual D-type flip-flop with set and reset;
positive edge-trigger
Product specification
74LV74
PIN CONFIGURATION
1RD 1
1D 2
1CP 3
1SD 4
1Q 5
1Q 6
GND 7
14 VCC
13 2RD
12 2D
11 2CP
10 2SD
9 2Q
8 2Q
LOGIC SYMBOL (IEEE/IEC)
4S
3 C1
2 1D
1R
10 S
11 C2
12 2D
13 R
SV00330
5
6
9
8
SV00332
LOGIC SYMBOL
4 10
1SD 2SD
2 1D
12 2D
3 1CP
11 2CP
SD
DQ
CP FF
Q
RD
1Q
2Q
1Q
2Q
5
9
6
8
1RD 2RD
1 13
SV00331
FUNCTIONAL DIAGRAM
4 1SD
2 1D
SD
DQ
3 1CP CP FF1
Q
1Q 5
1Q 6
1 1RD
10 2SD
RD
12 2D
SD
DQ
11 2CP CP FF2
Q
2Q 9
2Q 8
13 2RD
RD
SV00333
1998 Apr 20
3










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