74LVC109 PDF даташит
Спецификация 74LVC109 изготовлена «Philips» и имеет функцию, называемую «Dual JK flip-flop with set and reset; positive-edge trigger». |
|
Детали детали
Номер произв | 74LVC109 |
Описание | Dual JK flip-flop with set and reset; positive-edge trigger |
Производители | Philips |
логотип |
10 Pages
No Preview Available ! |
INTEGRATED CIRCUITS
74LVC109
Dual JK flip-flop with set and reset;
positive-edge trigger
Product specification
Supersedes data of 1997 Mar 18
IC24 Data Handbook
1998 Apr 28
Philips
Semiconductors
No Preview Available ! |
Philips Semiconductors
Dual JK flip-flop with set and reset; positive-edge trigger
Product specification
74LVC109
FEATURES
• Wide supply voltage range of 1.2 to 3.6 V
• In accordance with JEDEC standard no. 8-1A.
• Inputs accept voltages up to 5.5 V
• CMOS low power consumption
• Direct interface with TTL levels
• Output capability: standard
• ICC category: flip-flops
DESCRIPTION
The 74LVC109 is a low-voltage Si-gate CMOS device that is pin and
function compatible with 74HC/HCT109.
The 74LVC109 is a dual positive-edge triggered JK-type flip-flop
featuring individual J, K inputs, clock (CP) inputs, set (SD) and reset
(RD) inputs; also complementary Q and Q outputs.
The set and reset are asynchronous active LOW inputs and operate
independently of the clock input.
The J and K inputs control the state changes of the flip-flops as
described in the mode select function table. The J and K inputs must
be stable one set-up time prior to the LOW-to-HIGH clock transition
for predictable operation. The JK design allows operation as a
D-type flip-flop by tying the J and K inputs together.
Schmitt-trigger action in the clock input makes the circuit highly
tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns
SYMBOL
PARAMETER
CONDITIONS
tPHL/tPLH
Propagation delay
nCP to nQ, nQ
nSD to nQ, nQ
nRD to nQ, nQ
CL = 50 pF;
VCC = 3.3 V
fmax Maximum clock frequency
CI Input capacitance
CPD Power dissipation capacitance per flip-flop VI = GND to VCC1
NOTE:
1. CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD × VCC2 × fi )Σ (CL × VCC2 × fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
Σ (CL × VCC2 × fo) = sum of the outputs.
TYPICAL
4.0
4.5
4.5
250
5.0
27
ORDERING INFORMATION
PACKAGES
16-Pin Plastic SO
16-Pin Plastic SSOP Type II
16-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74LVC109 D
74LVC109 DB
74LVC109 PW
NORTH AMERICA
74LVC109 D
74LVC109 DB
74LVC109PW DH
UNIT
ns
MHz
pF
pF
PKG. DWG. #
SOT109-1
SOT338-1
SOT403-1
PIN CONFIGURATION
1RD 1
1J 2
1K 3
1CP 4
1S D 5
1Q 6
1Q 7
GND 8
16 VCC
15 2R D
14 2J
13 2K
12 2CP
11 2SD
10 2Q
9 2Q
SV00517
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
FUNCTION
1, 15
1RD, 2RD
Asynchronous reset input
(active LOW)
2, 14, 3, 13
1J, 2J, 1K, 2K
Synchronous inputs;
flip-flops 1 and 2
4, 12
1CP, 2CP
Clock input
(LOW-to-HIGH, edge-triggered)
5, 11
1SD, 2SD
Asynchronous set inputs
(active LOW)
6, 10
1Q, 2Q
True flip-flop outputs
7, 9
1Q, 2Q
Complement flip-flop outputs
8
GND
Ground (O V)
16 VCC
Positive supply voltage
1998 Apr 28
2 853–1947 19308
No Preview Available ! |
Philips Semiconductors
Dual JK flip-flop with set and reset; positive-edge trigger
Product specification
74LVC109
LOGIC SYMBOL (IEEE/IEC)
5
S
2
1J
4
C1
3
1K
1
R
11
6 14
12
7 13
15
(a)
S
10
1J
C1
1K
9
R
(b)
SV00519
LOGIC SYMBOL
5 11
1SD 2SD
2 1J J
14 2J
4 1CP
CP
12 2CP
3 1K
K
13 2K
1Q 6
Q
2Q 10
1Q 7
Q
2Q 9
FUNCTIONAL DIAGRAM
5 1SD
SD
2
1J
J
Q 1Q 6
4
1CP
CP
3
1K
K
FF1
Q 1Q 7
1 1RD
RD
11 2SD
SD
14 2J J
Q 2Q 10
12 2CP CP
13 2K K
FF2
2Q
Q
9
15 2RD
RD
SV00520
1R D 2RD
1 15
SV00518
LOGIC DIAGRAM
K
J
S
R
CP
CC
CC
C
C
CC
CC
Q
Q
SV00521
1998 Apr 28
3
Скачать PDF:
[ 74LVC109.PDF Даташит ]
Номер в каталоге | Описание | Производители |
74LVC10 | Triple 3-input NAND gate | Philips |
74LVC109 | Dual JK flip-flop with set and reset; positive-edge trigger | Philips |
74LVC10A | Triple 3-input NAND gate | Philips |
74LVC10D | Triple 3-input NAND gate | Philips |
Номер в каталоге | Описание | Производители |
TL431 | 100 мА, регулируемый прецизионный шунтирующий регулятор |
Unisonic Technologies |
IRF840 | 8 А, 500 В, N-канальный МОП-транзистор |
Vishay |
LM317 | Линейный стабилизатор напряжения, 1,5 А |
STMicroelectronics |
DataSheet26.com | 2020 | Контакты | Поиск |