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74LVC169 PDF даташит

Спецификация 74LVC169 изготовлена ​​​​«Philips» и имеет функцию, называемую «Presettable synchronous 4-bit up/down binary counter».

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Номер произв 74LVC169
Описание Presettable synchronous 4-bit up/down binary counter
Производители Philips
логотип Philips логотип 

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74LVC169 Даташит, Описание, Даташиты
INTEGRATED CIRCUITS
74LVC169
Presettable synchronous 4-bit up/down
binary counter
specification
Supersedes data of 1996 Aug 23
IC24 Data Handbook
1998 May 20
Philips
Semiconductors









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74LVC169 Даташит, Описание, Даташиты
Philips Semiconductors
Presettable synchronous 4-bit up/down
binary counter
Product specification
74LVC169
FEATURES
Wide supply voltage range of 1.2 V to 3.6 V
In accordance with JEDEC standard no. 8-1A
Inputs accept voltages up to 5.5 V
CMOS low power consumption
Direct interface with TTL levels
Synchronous counting and loading
Up/down counting
Modular 16 binary counter
Two count enable inputs for n-bit cascading
Built-in lookahead carry capability
Presettable for programmable operation
Positive-edge triggered clock
DESCRIPTION
The 74LVC169 is a high-performance, low-power, low-voltage,
Si-gate CMOS device and superior to most advanced CMOS
compatible TTL families.
The 74LVC169 is a synchronous presettable binary counter which
features an internal lookahead carry and can be used for high-speed
counting. Synchronous operation is provided by having all flip-flops
clocked simultaneously on the positive-going edge of the clock (CP).
The outputs (Q0 to Q3) of the counters may be preset to a HIGH or
LOW level. A LOW level at the parallel enable input (PE) disables
the counting action and causes the data at the data inputs
(D0 to D3) to be loaded into the counter on the positive-going edge
of the clock (provided that the set-up and hold time requirements for
PE are met). Preset takes place regardless of the levels at count
enable inputs (CEP and CET). A low level at the master reset input
(MR) sets all four outputs of the flip-flops (Q0 to Q3) to LOW level
after the next positive-going transition on the clock (CP) input
(provided that the set-up and hold time requirements for PE are
met).
This action occurs regardless of the levels at CP, PE, CET and CEP
inputs This synchronous reset feature enables the designer to
modify the maximum count with only one external NAND gate.
The lookahead carry simplifies serial cascading of the counters.
Both count enable inputs (CEP and CET) must be HIGH to count.
The CET input is fed forward to enable the terminal count output
(TC). The TC output thus enabled will produce a HIGH output pulse
of a duration approximately equal to a HIGH level output of Q0. This
pulse can be used to enable the next cascaded stage. The
maximum clock frequency for the cascaded counters is determined
by the CP to TC propagation delay and CEP to CP set-up time,
according to the following formula:
fmax =
________________1_______________
tp(max) (CP to TC) + tSU (CEP to CP)
QUICK REFERENCE DATA
GND = 0V; Tamb = 25°C; TR = TF  2.5ns
SYMBOL
PARAMETER
tPHL/tPLH
Propagation delay
CP to Qn
CP to TC
CET to TC
fMAX
maximum clock frequency
CI input capacitance
CPD power dissipation capacitance per gate
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD x VCC2 x fi +Σ (CL x VCC2 x fo ) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
Σ (CL x VCC2 x fo ) = sum of the outputs
2. The condition is V1 = GND to VCC
CONDITIONS
CL = 50 pF
VCC = 3.3V
notes 1 and 2
TYPICAL
5.0
6.5
5.3
200
5.0
42
UNIT
ns
MHz
pF
pF
ORDERING INFORMATION
PACKAGES
16-Pin Plastic SO
16-Pin Plastic SSOP Type II
16-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74LVC169 D
74LVC169 DB
74LVC169 PW
NORTH AMERICA
74LVC169 D
74LVC169 DB
74LVC169PW DH
DWG NUMBER
SOT109-1
SOT338-1
SOT403-1
1998 May 20
2 853-1866 19421









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74LVC169 Даташит, Описание, Даташиты
Philips Semiconductors
Presettable synchronous 4-bit up/down
binary counter
Product specification
74LVC169
PIN CONFIGURATION
U/D 1
CP 2
D0 3
D1 4
D2 5
D3 6
CEP 7
GND 8
16 VCC
15 TC
14 Q0
13 Q1
12 Q2
11 Q3
10 CET
9 PE
SF00766
LOGIC SYMBOL
9 PE
1 U/D
2 CP
7 CEP
10 CET
3456
D0 D1 D2 D3
TC
Q0 Q1 Q2 Q3
15
VCC = Pin 16
GND = Pin 8
14 13 12 11
SF00786
PIN DESCRIPTION
PIN NUMBER
SYMBOL
1 U/D
2 CP
3,4,5,6
7
D0 to D3
CEP
8 GND
9 PE
10
14,13,12,11
15
16
CET
Q0 to Q3
TC
VCC
FUNCTION
up/down control input
clock input (LOW-to-HIGH,
edge-triggered)
data inputs
count enable inputs (active
LOW)
ground (0V)
parallel enable input
(active LOW)
count enable carry input
(active LOW)
flip-flop outputs
terminal count output
(active LOW)
positive supply voltage
LOGIC SYMBOL (IEEE/IEC)
CTR DIV 16
9
M1 [LOAD]
M2 [COUNT]
1 M3 [UP]
M4 [DOWN]
10 G5
3, 5 CT=15
15
7 G6
4, 5 CT=0
2 2, 3, 5, 6+/C7
2, 4, 5, 6–
3
1, 7D
[1]
4 [2]
5 [4]
6 [8]
14
13
12
11
SF00787
1998 May 20
3










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