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74LVC1G00 PDF даташит

Спецификация 74LVC1G00 изготовлена ​​​​«Philips» и имеет функцию, называемую «Single 2-input NAND gate».

Детали детали

Номер произв 74LVC1G00
Описание Single 2-input NAND gate
Производители Philips
логотип Philips логотип 

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74LVC1G00 Даташит, Описание, Даташиты
INTEGRATED CIRCUITS
DATA SHEET
74LVC1G00
Single 2-input NAND gate
Product specification
Supersedes data of 2000 Nov 08
File under Integrated Circuits, IC24
2001 Apr 05









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74LVC1G00 Даташит, Описание, Даташиты
Philips Semiconductors
Single 2-input NAND gate
Product specification
74LVC1G00
FEATURES
Wide supply voltage range from 1.65 to 5.5 V
High noise immunity
Complies with JEDEC standard:
– JESD8-7 (1.65 to 1.95 V)
– JESD8-5 (2.3 to 2.7 V)
– JESD8B/JESD36 (2.7 to 3.6 V).
• ±24 mA output drive (VCC = 3.0 V)
CMOS low power consumption
Latch-up performance 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
SOT353 package.
DESCRIPTION
The 74LVC1G00 is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 or 5 V devices. This
feature allow the use of these devices in a mixed
3.3 and 5 V environment.
Schmitt-trigger action at all inputs makes the circuit
tolerant for slower input rise and fall time.
This device is fully specified for partial power-down
applications using Ioff. The Ioff circuitry disables the output,
preventing the damaging current backflow through the
device when it is powered down.
The 74LVC1G00 provides the single 2-input NAND
function.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf 2.5 ns.
SYMBOL
PARAMETER
tPHL/tPLH propagation delay inputs A and B to
output Y
CI input capacitance
CPD power dissipation capacitance per buffer
CONDITIONS
VCC = 1.8 V; CL = 30 pF; RL = 1 k
VCC = 2.5 V; CL = 30 pF; RL = 500
VCC = 2.7 V; CL = 30 pF; RL = 500
VCC = 3.3 V; CL = 50 pF; RL = 500
VCC = 5.0 V; CL = 50 pF; RL = 500
VCC = 3.3 V; notes 1 and 2
TYPICAL UNIT
3.3 ns
2.2 ns
2.6 ns
2.2 ns
1.8 ns
5 pF
14 pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
2. The condition is VI = GND to VCC.
2001 Apr 05
2









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74LVC1G00 Даташит, Описание, Даташиты
Philips Semiconductors
Single 2-input NAND gate
Product specification
74LVC1G00
FUNCTION TABLE
See note 1.
A
L
L
H
H
Note
1. H = HIGH voltage level;
L = LOW voltage level.
INPUT
B
L
H
L
H
OUTPUT
Y
H
H
H
L
ORDERING INFORMATION
TYPE NUMBER
74LVC1G00GW
TEMPERATURE
RANGE
40 to +85 °C
PINS
5
PACKAGE
PACKAGE MATERIAL
SC-88A
plastic
CODE
SOT353
MARKING
VA
PINNING
PIN
1
2
3
4
5
SYMBOL
B
A
GND
Y
VCC
data input B
data input A
ground (0 V)
data output Y
supply voltage
DESCRIPTION
handbook, halfpage
B1
A2
GND 3
5 VCC
00
4Y
MNA096
Fig.1 Pin configuration.
2001 Apr 05
handbook, halfpage
1B
2A
Y4
MNA097
Fig.2 Logic symbol.
3










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Номер в каталогеОписаниеПроизводители
74LVC1G00Single 2-input NAND gatePhilips
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74LVC1G02SINGLE 2 INPUT POSITIVE NOR GATEDiodes
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