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74LVC1G58 PDF даташит

Спецификация 74LVC1G58 изготовлена ​​​​«NXP Semiconductors» и имеет функцию, называемую «Low-power configurable multiple function gate».

Детали детали

Номер произв 74LVC1G58
Описание Low-power configurable multiple function gate
Производители NXP Semiconductors
логотип NXP Semiconductors логотип 

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74LVC1G58 Даташит, Описание, Даташиты
74LVC1G58
Low-power configurable multiple function gate
Rev. 01 — 15 September 2004
Product data sheet
1. General description
The 74LVC1G58 is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this
device in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using Ioff. The Ioff circuitry
disables the output, preventing the damaging backflow current through the device when it
is powered down.
The 74LVC1G58 provides configurable multiple functions. The output state is determined
by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,
NOR, XOR, inverter and buffer. All inputs can be connected to VCC or GND.
The three inputs (A, B and C) are capable of transforming slowly changing input signals
into sharply defined, jitter-free output signals.
The gate switches at different points for positive and negative-going signals. The
difference between the positive voltage VT+ and the negative voltage VTis defined as the
hysteresis voltage VH.
2. Features
s Wide supply voltage range from 1.65 V to 5.5 V
s 5 V tolerant input/output for interfacing with 5 V logic
s High noise immunity
s Complies with JEDEC standard:
x JESD8-7 (1.65 V to 1.95 V)
x JESD8-5 (2.3 V to 2.7 V)
x JESD8B/JESD36 (2.7 V to 3.6 V).
s ±24 mA output drive (VCC = 3.0 V)
s ESD protection:
x HBM EIA/JESD22-A114-B exceeds 2000 V
x MM EIA/JESD22-A115-A exceeds 200 V.
s CMOS low power consumption
s Latch-up performance exceeds 250 mA
s Direct interface with TTL levels
s Inputs accept voltages up to 5 V
s Multiple package options
s Specified from 40 °C to +85 °C and 40 °C to +125 °C.









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74LVC1G58 Даташит, Описание, Даташиты
Philips Semiconductors
74LVC1G58
Low-power configurable multiple function gate
3. Quick reference data
Table 1: Quick reference data
GND = 0 V; Tamb = 25 °C; tr = tf 2.5 ns.
Symbol Parameter
Conditions
Min Typ Max Unit
tPHL, tPLH propagation delay
input A, B and
C to output Y
CI input capacitance
CPD power dissipation
capacitance per buffer
VCC = 1.8 V; CL = 30 pF;
RL = 1 k
VCC = 2.5 V; CL = 30 pF;
RL = 500
VCC = 2.7 V; CL = 50 pF;
RL = 500
VCC = 3.3 V; CL = 50 pF;
RL = 500
VCC = 5.0 V; CL = 50 pF;
RL = 500
VCC = 3.3 V
-
-
-
-
-
-
[1] [2] -
6-
3.5 -
4.2 -
3.8 -
3.0 -
2.5 -
20 -
ns
ns
ns
ns
ns
pF
pF
[1] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
[2] The condition is VI = GND to VCC.
4. Ordering information
Table 2: Ordering information
Type number
Package
Temperature range
74LVC1G58GW 40 °C to +125 °C
74LVC1G58GV 40 °C to +125 °C
74LVC1G58GM 40 °C to +125 °C
5. Marking
Name
SC-88
SC-74
XSON6
Description
plastic surface mounted package; 6 leads
plastic surface mounted package; 6 leads
plastic extremely thin small outline package; no
leads; 6 terminals; body 1 × 1.45 × 0.5 mm
Version
SOT363
SOT457
SOT886
Table 3: Marking
Type number
74LVC1G58GW
74LVC1G58GV
74LVC1G58GM
Marking code
YK
V58
YK
9397 750 13852
Product data sheet
Rev. 01 — 15 September 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
2 of 18









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74LVC1G58 Даташит, Описание, Даташиты
Philips Semiconductors
6. Functional diagram
74LVC1G58
Low-power configurable multiple function gate
Fig 1. Logic symbol.
7. Pinning information
A3
B1
C6
7.1 Pinning
4Y
001aab687
58
B1
6C
B1
6C
GND 2 58 5 VCC
GND 2
5 VCC
A3
4Y
001aab686
A3
4Y
001aab731
Transparent top view
Fig 2. Pin configuration SC-88 and SC-74. Fig 3. Pin configuration XSON6.
7.2 Pin description
Table 4:
Symbol
B
GND
A
Y
VCC
C
Pin description
Pin
1
2
3
4
5
6
Description
data input B
ground (0 V)
data input A
data output Y
supply voltage
data input C
9397 750 13852
Product data sheet
Rev. 01 — 15 September 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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